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系統識別號 U0026-3010201921585100
論文名稱(中文) 混合式記憶體之負載平衡及箱感知方法之設計與實作
論文名稱(英文) Design and Implementation of a Load Balancing and Bin-Aware Mechanism for Hybrid Main Memories
校院名稱 成功大學
系所名稱(中) 資訊工程學系
系所名稱(英) Institute of Computer Science and Information Engineering
學年度 108
學期 1
出版年 108
研究生(中文) 陳慶任
研究生(英文) Ching-Ren Chen
學號 P76061271
學位類別 碩士
語文別 英文
論文頁數 34頁
口試委員 指導教授-張大緯
口試委員-張軒彬
口試委員-曾秀松
中文關鍵字 混合式記憶體  負載平衡  效能  相變化記憶體  再新 
英文關鍵字 Hybrid memory  Load balance  Performance  PCM  Refresh 
學科別分類
中文摘要 由於相變化記憶體 (PCM) 高容量及低閒置功耗的特性,使得它有希望取代動態隨機記憶體作為主記憶體。然而,相變化記憶體要完全取代動態隨機記憶體還需要克服兩個缺點(慢寫入延遲以及低寫入次數限制)。為了擷取兩者的優點,先前的研究採用小容量動態隨機記憶體及大容量相變化記憶體組成混合式記憶體。常見的混合式記憶體架構把動態隨機記憶體當作相變化記憶體的快取,或者把動態隨機記憶體及相變化記憶體接當作主記憶體使用。不管是哪種架構,現有的資料擺放方法皆會造成負載不平衡因為這些方法皆沒有考慮動態隨機記憶體及相變化記憶體的負載問題。
本論文提出一個新的資料擺放方法來處理這個問題,稱為Taiji。本方法週期性紀錄頁面存取資訊以及動態從過載控制器搬移頁面到另一個控制器來有效管理動態隨機記憶體及相變化記憶體來達到負載平衡。根據實驗結果,本方法相較於WIRD效能改善19.0% 且搬移成本平均只有1.8%。
英文摘要 Phase change memory (PCM) has recently emerged as a promising technology to substitute DRAM due to its high capacity and low standby energy. However, PCM has two shortcomings (slow-write access latency and less write endurance) to totally replace DRAM. To take merits of both DRAM and PCM, prior work has investigated hybrid memory systems consisting of a small DRAM and a large PCM. The common types of hybrid memory systems in prior works are using DRAM as cache, or using it as part of main memory. No matter in which type, the existing data placement methods could cause load imbalance problem, because the utilities (load) of DRAM and PCM are not under consideration.
In this paper, we proposed a new page placement method called Taiji to address this problem. Our Taiji effectively manages fast (DRAM) and slow (PCM) memory to reach load balance. To achieve this, Taiji records memory page access information, observes the load of the memory controllers, and then dynamically migrate pages from the overloading controller to the other one periodically. Based on experiment results, our Taiji improve performance by 19.0% over WIRD on average, and the migration time overhead is only 1.8% on average.
論文目次 摘要 I
ABSTRACT II
致謝 III
CONTENT IV
LIST OF TABLES VI
LIST OF FIGURES VII
Chapter 1 INTRODUCTION 1
Chapter 2 BACKGROUND 3
2.1 Row Buffer in Memory 3
2.2 Subarray in DRAM 3
2.3 DRAM Refresh 4
Chapter 3 RELATED WORK 5
3.1 Modeling DRAM as cache to PCM 5
3.2 Modeling DRAM as part of main memory 6
3.2.1 OS-managed 6
3.2.2 HW-managed 6
Chapter 4 DESIGN of TAIJI 8
4.1 Balance determination 9
4.1.1 Computing the average access latency 11
4.1.2 Computing the average queue length 11
4.2 Determinating the number of migration page 12
4.2.1 Computing the D-value of page 13
4.2.2 Computing the Impact(P) 13
4.2.3 Migration policy 16
4.3 Bin-aware refresh 20
4.3.1 Refresh flow 20
4.3.2 Group pages into Bins 21
Chapter 5 PERPFRMANCE RESULT 23
5.1 Simulation Environment 23
5.2 Performance 24
5.3 Hardware Overhead 29
Chapter 6 CONCLUSION 31
REFERENCES 32
參考文獻 K. Kim, “Future memory technology: challenges and opportunities,” in the Proceedings of International Symposium on VLSI Technology, Systems and Applications, Taiwan, 2008, pp. 5-9.
[2] S. K. Park, “Technology Scaling Challenge and Future Prospects of DRAM and NAND Flash Memory,” in the Proceedings of IEEE International Memory Workshop, USA, 2015, pp. 1-4.
[3] O. Mutlu, Main Memory Scaling: Challenges and Solution Directions. CMU, USA, 2015.
[4] Y. Kim, V. Seshadri, D. Lee, J. Liu, and O. Mutlu, “A case for exploiting subarray-level parallelism (SALP) in DRAM,” in the Proceedings of the 39th Annual International Symposium on Computer Architecture, USA, 2012, pp. 368-379.
[5] P. Zhou, B. Zhao, J. Yang, and Y. Zhang, “A durable and energy efficient main memory using phase change memory technology,” in Proceedings of the 36th annual international symposium on Computer architecture, USA, 2009, pp. 14–23.
[6] B. C. Lee, P. Zhou, J. Yang, Y. Zhang, B. Zhao, E. Ipek, O. Mutlu, and D. Burger, “Phase-change technology and the future of main memory,” IEEE Micro, vol. 30, no. 1, pp. 143–143, Mar. 2010, DOI. 10.1109/MM.2010.24.
[7] B. C. Lee, E. Ipek, O. Mutlu, and D. Burger, “Architecting phase change memory as a scalable DRAM alternative,” in Proceedings of the 36th annual international symposium on Computer architecture, USA, 2009, pp. 2–13.
[8] M. K. Qureshi, V. Srinivasan, and J. A. Rivers, “Scalable high performance main memory system using phase-change memory technology,” in Proceedings of the 36th annual international symposium on Computer architecture, USA, 2009, pp. 14–23.
[9] H. Yoon, J. Meza, R. Ausavarungnirun, R. A. Harding, and O. Mutlu, “Row buffer locality aware caching policies for hybrid memories,” in Proceedings of the 30th International Conference on Computer Design, Canada, 2012, pp. 337-344.
[10] L. Ramos, E. Gorbatov, and R. Bianchini, “Page placement in hybrid memory systems,” in Proceedings of the 23th international conference on Supercomputing, USA, 2011, pp. 85-95.
[11] G. Dhiman, R. Ayoub, and T. Rosing, “PDRAM: A hybrid PRAM and DRAM main memory system,” in Proceedings of the 46th Design Automation Conference, USA, 2009, pp. 664–669.
[12] S. Lee, H. Bahn, and S. H. Noh, “CLOCK-DWF: A write-history aware page replacement algorithm for hybrid PCM and DRAM memory architectures,” IEEE Transactions on Computers, vol. 63, no. 9, pp. 2187–2200, Sept. 2014, DOI. 10.1109/TC.2013.98.
[13] N. Niu, F. Fu, B. Yang, J. Yuan, F. Lai, and J. Wang, “WIRD: An Efficiency Migration Scheme in Hybrid DRAM and PCM Main Memory for Image Processing Applications,” IEEE Access, vol. 7, pp. 35941–35951, Mar. 2019, DOI. 10.1109/ACCESS.2019.2904803.
[14] J. Sim, A. R. Alameldeen, Z. Chishti, C. Wilkerson, and H. Kim, “Transparent Hardware Management of Stacked DRAM as Part of Memory,” in Proceedings of 47th Annual IEEE/ACM International Symposium on Microarchitecture, USA, 2014, pp. 13-24.
[15] D. Knyaginin, V. Papaefstathiou, and P. Stenstrom, “ProFess: A Probabilistic Hybrid Main Memory Management Framework for High Performance and Fairness,” IEEE International Symposium on High Performance Computer Architecture, Feb. 2018, DOI. 10.1109/HPCA.2018.00022.
[16] J. Liu, B. Jaiyen, R. Veras, and O. Mutlu, “RAIDR: Retention-aware intelligent DRAM refresh,” in Proceedings of the 39th Annual International Symposium on Computer Architecture, USA, 2012, pp. 1-12.
[17] S. Liu, K. Pattabiraman, T. Moscibroda, and B. G. Zorn, “Flikker: Saving DRAM refresh-power through critical data partitioning,” in Proceedings of the 16th International Conference on Architectural Support for Programming Languages and Operating Systems, USA, 2011, pp. 213-224.
[18] A. Agrawal, M. O'Connor, E. Bolotin, N. Chatterjee, J. Emer, and S. Keckler, “CLARA: Circular linked-list auto and self refresh architecture,” in Proceedings of the 2nd International Symposium on Memory Systems, USA, 2016, pp. 338-349.
[19] I. Bhati, Z. Chishti, S. L. Lu, and B. Jacob, “Flexible auto-refresh: Enabling scalable and energy-efficient DRAM refresh reductions,” in Proceedings of the 42nd Annual International Symposium on Computer Architecture, USA, 2015, pp. 235-246.
[20] I. Bhati, M.-T. Chang, Z. Chishti, S.-L. Lu, and B. Jacob, “DRAM refresh mechanisms, penalties, and trade-offs,” IEEE Transactions on Computers, vol. 65, no. 1, pp. 108-121, Jan. 2016, DOI. 10.1109/TC.2015.2417540.
[21] DDR4 SDRAM, JESD79-4B, Nov. 2015.
[22] Python, “lfudacache, an implementation of Less Frequently Used with Dynamic Aging (LFUDA),” Oct. 2017. [Online] Available: https://pypi.org/project/lfudacache/0.0.1/
[23] N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M. D. Hill, and D. A. Wood, “The GEM5 simulator,” SIGARCH Computer Architecture News, vol. 39, no. 2, pp. 1-7, May 2011, DOI. 10.1145/2024716.2024718.
[24] “Micron DDR4 SDRAM Part MT40A512M16,” Micron Technology Inc., 2015. Micron Inc.
[25] Y. Zhou, J. F. Philbin, and K. Li, “The multi-queue replacement algorithm for second level buffer caches,” in Proceedings of the Usenix Technical Conference, USA, 2001, pp. 91-104.
[26] Micron Technology Inc., “Breakthrough Nonvolatile Memory Technology,” 2016. [Online] available: https://www.micron.com/about/our-innovation/3d-xpoint-technology.
[27] J, Bucek, K. D. Lange, and J. Kistowski, “SPEC CPU2017 – Next-Generation Compute Benchmark”, in the Proceedings of 9th International Conference on Performance Engineering, Germany, 2018, pp. 41-42.
[28] D. H. Bailey, E. Barszcz, J. T. Barton, D. S. Browning, R. L. Carter, L. Dagum, R. A. Fatoohi, P. O. Frederickson, T. A. Lasinski, R. S. Schreiber, H. D. Simon, V. Venkatakrishnan, and S. K. Weeratunga, “The NAS parallel benchmarks,” in Proceedings of the ACM/IEEE Conference on Supercomputing, USA, 1991, pp. 158–165.
[29] S. Beamer, K. Asanovi´c, and D. Patterson, “The gap benchmark suite,” CoRR, vol. abs/1508.03619, 2015. [Online]. Available: https://arxiv.org/abs/1508.03619
[30] M. Mulkalapally, J. Manning, P. Gatewood, and T. Nikoubin, “High Speed, Area and Power Efficient 32-bit Vedic Multipliers,” in the Proceedings of 7th International Conference on Computing Communication and Networking Technologies, USA, 2016, pp. 11.
[31] Intel technology, Inc., “Quartus, a FPGA development tool,” Sep. 2018. [Online] Available: http://fpgasoftware.intel.com/?edition=lite
[32] J. Izraelevitz, J. Yang, L. Zhang, J. Kim, X. Liu, A. Memaripour, Y. J. Soh, Z. Wang, Y. Xu, S. R. Dulloor, J. Zhao, and S. Swanson. 2019. Basic performance measurements of the Intel Optane DC persistent memory module. Retrieved from: CoRR abs/1903.05714.
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