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系統識別號 U0026-3007201318593900
論文名稱(中文) 應用於24 GHz雷達系統之低功耗壓控振盪器和降頻混頻器電路設計
論文名稱(英文) Circuit Design of Low-Power Voltage-Controlled Oscillator and Down-Conversion Mixer for 24 GHz Radar Systems
校院名稱 成功大學
系所名稱(中) 電機工程學系碩博士班
系所名稱(英) Department of Electrical Engineering
學年度 101
學期 2
出版年 102
研究生(中文) 余紹萍
研究生(英文) Shao-Ping Yu
學號 n26000339
學位類別 碩士
語文別 英文
論文頁數 82頁
口試委員 指導教授-楊慶隆
口試委員-莊惠如
口試委員-黃尊禧
口試委員-蔡宗亨
中文關鍵字 壓控振盪器  鎖相迴路  混頻器  調頻連續波雷達 
英文關鍵字 VCO  PLL  Mixer  FMCW Radar 
學科別分類
中文摘要 本論文提出應用於24 GHz雷達系統之低功耗壓控振盪器和降頻混頻器電路設計,這些電路皆使用TSMC 1P6M CMOS 0.18 μm製程來實現,在不使用其他較昂貴的製程下,TSMC CMOS 0.18 μm製程仍然可讓電路操作在24 GHz時有不錯的效能表現。
本碩論主要分成兩個部份。第一個部份為壓控振盪器的設計,此壓控振盪器結合了Colpitts和current-reused架構來達到低功耗的效能,電路中主要藉由PMOS-NMOS組成的current-reused技術大幅降低VCO功耗並結合差動式Colpitts架構,進一步達到低功耗和改善相位雜訊。模擬結果顯示,當此VCO的工作電壓為1.8 V時,調頻範圍為22.72 GHz到24.55 GHz,相位雜訊為-102.8 dBc/Hz @ 1 MHz,VCO core的功率消耗為3 mW,FOM為 -185.8 dBc/Hz,晶片面積為0.62 mm2。
第二個部份的24 GHz低功耗降頻混頻器為Gilbert-cell架構,採用current-bleeding技術多增加一條電流路徑來控制切換級的電流,讓較高的增益可以通過較大的負載級電阻。此外,在轉導級的上方並聯一個電感,此電感和其他電晶體的寄生電容共振在RF頻率,模擬結果顯示轉換增益改善了6 dB,雜訊因子改善了7 dB。混頻器的核心功耗為4.8 mW,轉換增益為 3.5 dB,雜訊因子為 8.5 dB,RF到IF、LO到IF和LO到RF的隔離度分別大於44、62和59 dB,輸入1 dB壓縮點為-11.5 dBm,晶片面積為1.14 mm2。
根據上述的壓控振盪器和降頻混頻器,未來這兩個低功耗電路將應用在調頻連續波雷達系統,以實現一個低功耗、低成本的24 GHz雷達系統。
英文摘要 This thesis proposed the circuit design of a low-power voltage-controlled oscillator (VCO) and a down-conversion mixer for 24 GHz radar system. Those circuits are implemented in TSMC 1P6M 0.18 μm CMOS technology. Without using other more expensive process, those circuits still achieve a good performance at 24 GHz.
This thesis is mainly composed of two parts. In the first part, a design of low-power voltage-controlled oscillator is presented. Utilizing colpitts and current-reused topology achieves low power consumption. The simulation results show the tuning range of VCO is from 22.72 to 24.55 GHz at supply voltage of 1.8 V. Phase noise is -102.8 dBc/Hz at 1 MHz offset. The VCO core power consumption is 3 mW. FOM is -185.8 dBc/Hz. The chip area is 0.62 mm2.
The second part is a low-power down-conversion Gilbert-cell mixer. The mixer utilizes current-bleeding technique which adds an extra current path to control DC current of switch stage’s transistors. The current-bleeding technique allows larger conversion gain to pass higher resistors of load stage. Besides, a resonant inductor is shunt with other parasitic capacitors of transistors. The inductor and parasitic capacitors resonate at RF frequency range of interests. The simulation results show the resonant inductor improved 6 dB in conversion gain and 7 dB in noise figure. The core power consumption of mixer is 4.8 mW. Conversion gain is 3.5 dB and noise figure is 8.5 dB. RF to IF, LO to IF and LO to RF isolation are larger than 44, 62, 59 dB, respectively. Input P1dB is -11.5 dBm. The chip area is 1.14 mm2.
According to above descriptions of voltage-controlled oscillator and down-conversion Gilbert-cell mixer, those low-power circuits will apply for frequency-modulated continuous-wave radar and achieve a low-power and low-cost 24 GHz radar system in the future.
論文目次 Chapter 1 Introduction....................1
1.1 Background and Motivation....................1
1.2 Literature Survey....................2
1.3 Contribution....................3
1.4 Thesis Organization....................5
Chapter 2 Design of Low-power Voltage Controlled Oscillator for 24 GHz Radar System....................7
2.1 Introduction and Literature Review....................7
2.2 Design of a CMOS voltage controlled oscillator....................9
2.2.1 Circuit Design....................9
2.2.2 Simulated Results for PVT Variation....................17
2.2.3 Measurement Consideration....................22
2.2.4 Discussions....................22
2.2.5 Performance Comparison....................23
2.3 Summary....................24
Chapter 3 Design of 24 GHz Phase-locked Loop Using Divide-by-5 Prescaler for Multi-band Applications....................25
3.1 Introduction and Literature Review....................25
3.2 Design of 24 GHz Phase-Locked Loop Using Divide-by-5 Prescaler....................27
3.2.1 Circuit Design....................27
3.2.2 Simulated Results....................34
3.2.3 Measurement Consideration....................40
3.2.4 Measurement Results....................41
3.2.5 Discussions....................44
3.2.6 Performance Comparison....................44
3.3 Summary....................45
Chapter 4 Design of Low-Power Gilbert-cell Mixer for 24 GHz Radar System....................46
4.1 Introduction and Literature Review....................46
4.2 Design of 24 GHz Low Power Gilbert-cell Mixer....................47
4.2.1 Circuit Design....................47
4.2.2 Simulated Results....................50
4.2.3 Measurement Considerations....................57
4.2.4 Performance Comparison....................58
4.3 Summary....................59
Chapter 5 Conclusion and Future Prospects....................60
5.1 Conclusion....................60
5.1.1 Design of Low-power VCO for 24 GHz Radar System....................60
5.1.2 Design of 24 GHz PLL Using Divide-by-5 Prescaler....................60
5.1.3 Design of Low-Power Gilbert-cell Mixer for 24 GHz Radar System....................61
5.2 Future Prospects....................62
5.2.1 Design of Low-power VCO for 24 GHz Radar System....................62
5.2.2 Optimization of 24 GHz PLL Using Divide-by-5 Prescaler....................62
5.2.3 Optimization of Low-Power Gilbert-cell Mixer for 24 GHz Radar System....................62
REFERENCE....................64
Appendix A The Verification of Radar System....................68
A.1 Introduction....................68
A.2 Components Specification....................69
A.3 Procedure Design of Experiment....................74
Appendix B The Verification of Radar Module....................75
B.1 Principle of FMCW Radar....................75
B.2 Procedure Design of Experiment....................76
B.3 Measurement Results....................78
B.4 Summary....................82
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