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系統識別號 U0026-2908201920394700
論文名稱(中文) 高功率氮化鋁鎵/氮化鎵異質接面金屬-絕緣體-半導體-高電子遷移率電晶體與授體摻雜閘極-高電子遷移率電晶體關鍵技術開發
論文名稱(英文) Critical Process Development in Power AlGaN/GaN MIS-HEMTs and p-GaN HEMTs
校院名稱 成功大學
系所名稱(中) 奈米積體電路工程碩士學位學程
系所名稱(英) MS Degree Program on Nano-Integrated Circuit Engineering
學年度 107
學期 2
出版年 108
研究生(中文) 陳政成
研究生(英文) Zheng-Cheng Chen
學號 Q76061010
學位類別 碩士
語文別 英文
論文頁數 65頁
口試委員 口試委員-李耀仁
口試委員-蘇俊榮
口試委員-吳添立
口試委員-馬誠佑
指導教授-高國興
中文關鍵字 無金接觸  數位式蝕刻  金-氧-半高電子遷移率電晶體  授體摻雜高電子遷移率電晶體 
英文關鍵字 Au-free ohmic  Digital Etching  MIS-HEMT  P-GaN HEMT 
學科別分類
中文摘要 此篇論文詳細描述MIS-HEMT每一站的製程開發,並著重於無金接觸的討論,運用Transmission line Measurement (TLM)結構進行討論,內容包括: 1. 元件隔絕:透過離子佈植隔絕元件 2. 接觸蝕刻:長久以來對GaN蝕刻的問題一直存在著,因此在蝕刻方面特別引用數位式蝕刻的概念,防止傳統蝕刻的不穩定、不均勻、不平滑等問題,由AFM分析得到驗證 3. 蝕刻後表面缺陷復原:減少蝕刻造成的表面缺陷 4. 無金歐姆接觸:可避免表面粗糙、高溫退火、高成本等問題 5. P-GaN活化測試,並對元件進行分析ID-VG、C-V、崩潰電壓測試、可靠度測試。最後將製程套用至P-GaN gate HEMT進行討論。
傳統的蝕刻方法的蝕刻率難以控制且不穩定,同一個批內深度差可以達到20 nm,我們使用數位式蝕刻改善了蝕刻輪廓的粗糙度從2.32到1.03,穩定的蝕刻率0.93 nm/cycle被得到,同一回合的深度差在10 nm以內。對於良率和可靠度而言,數位式蝕刻的非展示很重要的。
元件在VD=5V時,ID(max)=133mA/mm和Ion/IOFF=104,介電層和元件的承受電壓分別是10 V和422 V,在2000秒的off-state加壓後導通電阻比和閾值電壓偏移的差異分別是3倍和0.58 V,在1000秒後的閘極6 V加壓後閾值電壓偏移了0.7V。
在此篇論文的後面,P-GaN gate HEMT成功地被製造,但元件卻顯示出空乏型元件的特性,這是由PECVD所沉積的Si3N4所導致,經由改變鈍化層材料後,增強型元件已經成功地被獲得。
英文摘要 In this thesis, we described in details process development for MIS-HEMT, focusing on the discussion of Au-free ohmic contact. Transmission line measurement (TLM) structure was adopted heavily to step analysis, including device isolation using implantation, digital etching concept to avoid instability, unevenness, roughness caused by traditional etching, etching profile recovery, Au-free ohmic contact and P-GaN active test. We have analyzed device characteristics, including I-V, C-V, breakdown voltage and reliability. And we discuss P-GaN HEMT as well.
We have improved the roughness caused by traditional etching from 2.32 to 1.03 nm using digital etching, where the stable etching is well-controlled at a rate of 0.93 nm/cycle. In the same etching depth, the etching depth difference using digital etching is below 10 nm better than the traditional etching is 20 nm. For yield and reliability, development in digital etching is apparently important.
Our fabricated device shows the maximum drain current ID(max)=133mA/mm and on-off ratio ION/IOFF=104 at drain bias VD=5V. The voltage of the dielectric layer breakdown and device breakdown can achieve 10 V and 422 V, respectively. After 2000 sec off-state stress, on-resistance ratio and threshold voltage shift are 3 and 0.58 V, respectively. After 1000 sec gate stress with VG=6V, threshold voltage shifts 0.7 V.
In the last part of the thesis, the P-GaN gate HEMT has been fabricated successfully, but depletion-mode (D-mode) property is observed, which is due to Si3N4 deposited by PECVD. This reason has been verified by change passivation that gets enhancement-mode (E-mode).
論文目次 摘要 III
Abstract IV
Acknowledgment V
Content VI
Table captions VIII
Figure captions IX
I. Introduction 1
i. Material properties 1
1. Material 1
2. HEMT 3
ii. Enhancement mode (E-mode) technologies 4
1. P-GaN gate 4
2. Recessed gate with insulator 6
3. Others 7
iii. Ohmic contact on GaN HEMT 8
1. Gold and Au-free ohmic contact 8
2. Ti/Al ratio 10
3. Transmission line measurement (TLM) 12
II. Process 15
i. Isolation 15
1. Simulation 15
2. result 17
ii. Digital etching 22
1. Experiment 22
2. Discussion 24
iii. Surface treatment 28
iv. Au-free ohmic 29
1. Introduction 29
2. Measurement 30
v. P-GaN test 37
1. Method 37
2. Test 38
III. Fabrication 40
IV. Performance 46
i. ID-VG、CV characteristics 46
ii. Reliability 50
V. P-GaN gate HEMT fabrication and discussion 54
i. Fabrication 54
ii. Discussion 59
VI. Conclusion & Future work 62
i. Contact resistance 62
ii. Performance 62
iii. E-mode P-GaN HEMT 62
VII. Reference 63
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