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系統識別號 U0026-2808202010121700
論文名稱(中文) 在混和型凸塊陣列封裝內應用機率分析模型之多層逃脫繞線演算法
論文名稱(英文) Multilayer Escape Routing for Hybrid Bump Arrays in Package Using Probability Analysis Model
校院名稱 成功大學
系所名稱(中) 電機工程學系
系所名稱(英) Department of Electrical Engineering
學年度 108
學期 2
出版年 109
研究生(中文) 陳敬仁
研究生(英文) Jing-Ren Chen
學號 N26064765
學位類別 碩士
語文別 英文
論文頁數 40頁
口試委員 指導教授-林家民
口試委員-江蕙如
口試委員-李毅郎
口試委員-趙家佐
中文關鍵字 封裝繞線  逃脫繞線  凸塊陣列  繞線層分配 
英文關鍵字 package routing  escape routing  bump array  layer assignment 
學科別分類
中文摘要 隨著科技不斷進步,覆晶技術中的凸塊數量持續在增加,分布狀況也變得複雜且不規則,有時一個封裝設計中甚至存在一種以上的凸塊陣列形狀。然而,先前的研究主要專注於只含有一種凸塊陣列形狀的封裝設計,並且假設凸塊分布地非常均勻,這些研究的方法並不適用於現今產業界的設計。因此,本篇論文提出了一個基於機率分析模型的多層逃脫繞線演算法,其適用於混和型的凸塊陣列封裝設計。我們會先解析並區分不同形狀的凸塊陣列,然後使用一個基於繞線機率的方法來做每個訊號凸塊的逃脫繞線層分配。演算法也可以找到每層繞線層中每個凸塊陣列所適合的逃脫邊界,逃脫邊界是決定每個凸塊陣列在當層中可逃脫訊號的最大數量以及逃脫繞線方向的關鍵。除此之外,我們也提出了兩個新的網絡流模型來處理差分信號,還調整了一個先前著作的模型,以讓其可適用於新型的凸塊陣列結構。實驗結果顯示我們的演算法能適用並處理現今不斷變化的產業界封裝設計中的逃脫繞線問題。
英文摘要 As the technology advances, the bump number of a flip-chip keeps increasing. The distribution of bumps becomes more complex and irregular, sometimes there even exists more than one shape of bump array in a package. Previous researches focus on single shaped bump array and assume the distribution of bumps is quite uniform, it is not suitable for modern industrial designs. This paper proposes a probability-based multilayer escape routing algorithm for hybrid bump arrays package. We first distinguish different shapes of bump array, then use a routing probability-based method to do the layer assignment for every signal bump. The proposed algorithm will also find the suitable escape boundary for every bump array in each layer, which is the critical part that decide the maximum escape signal number and the routing direction of every bump array. We also proposed two network flow models to handle the differential pair signals and adjusted the model in [4] in order to suit the new shape of bump array. The experimental results show that our approach can handle the ever-changing industrial designs today.
論文目次 摘要 I
Abstract II
誌謝 III
Table of Contents IV
List of Tables VI
List of Figures VII
Chapter 1 Introduction 1
1.1 Previous Works 4
1.2 Our Contributions 5
1.3 Thesis Organization 6
Chapter 2 Preliminaries 7
2.1 Review of the Probabilistic Analysis Model 7
2.2 Review of Previous Network Flow Models 9
2.3 Definition of a tile in the BAs 11
Chapter 3 Multilayer Escape Routing Methodology 13
3.1 Overview of Our Methodology 13
3.2 Construction of Tile Graphs for Bump Arrays 14
3.3 Layer Assignment 16
3.3.1 Identification of the Escape Boundary and Tile Fence 16
3.3.2 Two-Phase Layer Assignment 21
3.4 Escape Routing 29
3.4.1 Network Flow Model for RBA 30
3.4.2 Network Flow Model for Differential Pairs in RBA 30
3.4.3 Network Flow Model for Differential Pairs in SBA 31
3.4.4 ILP Formulation 32
Chapter 4 Experimental Results 34
Chapter 5 Conclusion 38
Bibliography 39
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