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系統識別號 U0026-2608201122243900
論文名稱(中文) 半導體晶圓晶邊結構組成對良率之分析與研究
論文名稱(英文) A Study of Wafer Bevel Condition and Wafer Edge Yield Improvement
校院名稱 成功大學
系所名稱(中) 航空太空工程學系專班
系所名稱(英) Department of Aeronautics & Astronautics (on the job class)
學年度 99
學期 2
出版年 100
研究生(中文) 黃子政
研究生(英文) Tzu-Cheng Huang
學號 p4797107
學位類別 碩士
語文別 中文
論文頁數 44頁
口試委員 指導教授-高騏
口試委員-吳文端
口試委員-周正賢
中文關鍵字 晶邊良率 
英文關鍵字 wafer-edge 
學科別分類
中文摘要 隨著半導體製程的演進,晶圓由最先的四吋、六吋、八吋到目前的十二吋晶圓。晶圓尺吋越做越大,也帶來越來越多的技術挑戰,如製程中長膜的薄膜均勻度的掌控。而蝕刻技術的精進,雖然增加了蝕刻的深度,卻也帶來更多的難以清除的副產物(By-product),造成晶圓外圏良率越來越低。在元件尺吋不斷縮小,單位面積元件數目愈來愈多的情形下,晶圓外圈良率也越來越重要。由於晶圓良率和晶圓售價是成正比,所以晶圓外圈的良率改善在目前的產業獲利競爭中成為研究重點之ㄧ。
綜觀半導體晶圓產業界,針對晶邊良率改善有著相當多的研究及方法,如WEE (Wafer Edge Exposure)、EBR (Edge Bead Removal)等等,一切都針對著晶邊良率改善投入相當的資源研究。
本論文在晶圓製程中,除了觀察所發現到可能產生缺陷(Defect)的來源並加以分析成因,更針對材料間應力差異和後製程熱效應所產生Defect的結構,在Defect還未形成前,以新式的晶邊蝕刻技術(Bevel Etch, Bevel Strip),移除晶圓 Bevel (註1)薄膜沉積殘膜及蝕刻製程期間產生的副產物。並針對新式蝕刻製程的清潔能力與產品生產良率作交互比對。
研究結果發現,同一種產品中經過晶邊蝕刻技術處理過的晶圓,其晶圓外圈良率確實比未經過晶邊蝕刻技術處理過的來的高。以65奈米製程來說,晶圓外圈良率可以提升將近10%。
根據本實驗的結果,可以預期,若將實驗結果應用於四五奈米或未來的二八奈米製程上,半導體代工廠的製程良率可得到顯著的提升。
英文摘要 With advance in semiconductor fabrication, the size of silicon wafer gradually increases from 4 inches at the beginning use in industries, to 6 inches, 8 inches to nowadays 12 inches. The bigger size of silicon wafers brings more challenges to fabrication process, including precise control of uniformity in film deposition. The remarkable development in etching techniques, although, provides users to perform etching process with increment in etching depth, however, it also induces more by-products and lowers etching quality in the margin zone of wafers.
Quality in the margin zone of wafers is more and more important while the size of devices continuously shrinks and device density continuously enlarges. Due to product selling price is proportional to fabrication quality, worldwide manufacturing corporations strive to elevate fabrication quality in the margin zone of wafers.
Manufacturing corporations largely invest in numerous researches and methods trying to ameliorate fabrication quality in the margin zone, such as WEE and EBR methods.
In this study, we used novel wafer-edge etching technique to remove deposition impurities and by-products during process before development of defects attribute to stress difference between materials and thermal-induced structural flaw, which based on results of in advance observation and analysis of forming defects. We also analyzed effects of cleaning capability of novel etching technique on product quality.
The results show that margin zone quality after wafer-edge etching process is indeed better than wafer without treatment under other same controlled conditions. The margin zone quality could be improved up to 10% in 65-nm fabrication.
Based on the experimental outcome, application of this technique to 45-nm or further 28-nm fabrication, significant increase in fabrication quality and beneficial income can be expected eventually.
論文目次 目錄
授權書
簽署人須知
簽名頁
致謝
中文摘要
英文摘要
目錄……………………………………………………………………Ⅰ
圖目錄…………………………………………………………………Ⅲ
第一章 序論……………………………………………………………1
1.1 前言…………………………………………….…………1
1.2 研究動機與目的文獻回顧…………………….…………1
1.3 文獻回顧……………………………………….…………1
第二章 研究分析與手法………………………………………………3
2.1 現況分析………………………………………………………3
2.2 異常點分析……………………………………………………3
2.3 結構分析………………………………………………………4
第三章 實驗器具及方法………………………………………………5
3.1 實驗器具………………………………………………………5
3.1.1 APPLIED SEMVing 電子顯微鏡………………..…5
3.1.2 Bevel Etch Tool 晶邊蝕刻機…………………………5
3.1.3 KLA-Tencor缺陷檢驗機 ……………………………6
3.2 實驗方法………………………………………………………7
3.2.1 Bevel Etch…………………………………...…………7
3.2.2 Bevel Strip………………………………..……………7
第四章 實驗結果及良率分析…………………………………………8
4.1 實驗結果…………………………………….……………8
4.1.1 Bevel Etch對晶圓Bevel殘留薄膜去除…….………8
4.1.2 Bevel Strip對蝕刻副產物的改善……………………8
4.2 良率分析………………………………………….………9
4.2.1 對執行 Bevel Strip前針對Bevel 的觀察…….…9
4.2.2 對執行 Bevel Strip後針對 Bevel 的觀察………9
第五章 結論和未來展望………………………………….………9
5.1 結論………………………………………………….……9
5.2 未來展望…………………………………………………10
參考文獻……………………………………………………….………11
圖目錄……………………………………………………….…………15
註1 晶圓 Bevel ………………………………………………………15
Fig. 1-1-1本單位晶邊良率最外圈Zone3 良率比內圈低了10~15%...................................................................................................15
Fig. 2-1-1 本單位(A)委外代工(B)代工示意圖………...……….…..16
Fig. 2-1-2 本單位生產和代工晶圓 Wafer Bevel TEM 比較圖..…16
Fig. 2-1-3 In-line 檢驗data defect 分佈圖……………………….17
Fig. 2-1-4 Defect inline FIB (Focus Ion Beam) 示意圖………17
Fig. 2-2-1 晶邊逐站觀察 SEMV image-1…………..……..………..18
Fig. 2-2-2 晶邊逐站觀察 SEMV image-2…………………………..18
Fig. 2-2-3 晶邊逐站觀察 SEMV image-3…………………………..19
Fig. 2-2-4 晶圓 Bevel TEM 示意圖………………..…….………...19
Fig. 2-3-1 半導體薄膜材料應力分析圖……………………………..20
Fig. 2-3-2 晶圓薄膜裂開示意圖……………........…..…………..21
Fig. 2-3-3 晶邊缺陷SEM image…………………………..…….…..21
Fig. 2-3-4 In-line wafer edge defect TEM-1…………………….22
Fig. 2-3-5 In-line wafer edge defect TEM-2………………………22
Fig. 2-3-6 晶圓 Bevel 逐站觀察示意圖…………………..…….……23
Fig. 2-3-7 In-line 晶邊缺陷TEM-3………..……………………….23
Fig. 2-3-8 半導體薄膜材料應力分析………………………………..24
Fig. 3-1-1 APPLIED SEMVsion 機台示意圖…………………..….25
Fig. 3-1-2 光學顯微鏡示意圖………………………………..………25
Fig. 3-1-3 APPLIED SEMVsion 機台實體圖………………….…..26
Fig. 3-1-4 Bevel Etch機台示意圖………………….……..…………27
Fig. 3-1-5 Bevel Etch反應腔示意圖…………..………….…………27
Fig. 3-1-6 反應腔構造與反應氣體…………………..……..………..28
Fig. 3-1-7 電漿 (Plasma) 產生與反應邊界………….………….…28
Fig. 3-1-8 KLA-Tencor 缺陷檢驗機機台示意圖…………..………29
Fig. 3-1-9 機台成像方式示意圖…………….……………....………29
Fig. 3-1-10 機台影像比對方式………………………………………..30
Fig. 3-2-1 Bevel Etch效果示意圖…………………….….…………31
Fig. 3-2-2 產品經過Bevel Etch TEM示意圖-1…………..………..31
Fig. 3-2-3 產品經過 Bevel Etch TEM示意圖-2………...…..……..32
Fig. 3-2-4 產品經過 Bevel Etch TEM示意圖-3……..………..…..32
Fig. 3-2-5 產品Defect 示意圖………………….………………..…33
Fig. 3-2-6 Bevel Strip產品上運用效果示意圖…………...………..33
Fig. 4-1-1 未使用Bevel Etch前 Defect 狀況-1………….………..34
Fig. 4-1-2 未使用Bevel Etch前 Defect 狀況-2…………………...34
Fig. 4-1-3 未使用Bevel Etch前 Defect 狀況-3………….………..35
Fig. 4-1-4 未使用Bevel Etch前 Defect 狀況-4…………..……..35
Fig. 4-1-5 未使用Bevel Etch Wafer Bevel SEM image-1…………36
Fig. 4-1-6 未使用 Bevel Etch Wafer Bevel SEM image-2………36
Fig. 4-1-7 使用 Bevel Etch Wafer Bevel SEM image-1…………37
Fig. 4-1-8 使用 Bevel Etch後 Defect 狀況-1………………..…..37
Fig. 4-1-9 使用 Bevel Etch後 Defect 狀況-2……………….……..38
Fig. 4-1-10 使用Bevel Strip前 Bevel 狀況-1……………………….38
Fig. 4-1-11 使用 Bevel Strip前 Bevel 狀況-2………………….….39
Fig. 4-1-12 使用Bevel Strip前 Bevel 狀況-3……………………….39
Fig. 4-1-13 Bevel Strip實驗條件…………………………………….40
Fig. 4-1-14 Bevel Strip實驗結果-1……………….………………..40
Fig. 4-1-15 Bevel Strip實驗結果-2………………………..………..41
Fig. 4-1-16 Bevel Strip實驗前良率分析………………….……..….41
Fig. 4-1-17 Bevel Strip實驗後良率分析…………….….….……….42
Fig. 4-1-18 Bevel Strip實驗後長期良率分析…………………......42
Fig. 5-2-1 URAM 晶圓 Bevel SEMV 示意圖……………..……...43
Fig. 5-2-2 URAM晶圓Bevel在Bevel Etch前TEM 示意圖..…...43
Fig. 5-2-3 URAM晶圓Bevel在Bevel Etch後TEM 示意圖……..44
參考文獻 參考文獻
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[2] Taiki Murata, Masayuki Sato, “Reduction of wafer edge induced defect by WEE optimization, ISSM Paper: YE-P-230, IEEE, 2007.
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