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系統識別號 U0026-2607201303163800
論文名稱(中文) 應用於多標準多頻帶頻率合成器之低功率高效能CMOS振盪器設計與實現
論文名稱(英文) Design and Implementation of Low-Power High-Performance CMOS Oscillators for Multi-Standard/Multi-Band Frequency Synthesizers
校院名稱 成功大學
系所名稱(中) 電機工程學系碩博士班
系所名稱(英) Department of Electrical Engineering
學年度 101
學期 2
出版年 102
研究生(中文) 曾彥儒
研究生(英文) Yan-Ru Tseng
電子信箱 n2895132@mail.ncku.edu.tw
學號 n28951324
學位類別 博士
語文別 英文
論文頁數 118頁
口試委員 召集委員-湯敬文
口試委員-彭康峻
口試委員-楊慶隆
口試委員-吳建華
口試委員-廖育德
口試委員-莊惠如
指導教授-黃尊禧
中文關鍵字 低功率  多標準多頻帶  共存系統  載波產生器  頻率合成器  變壓器回授  變壓器耦合  電流再使用  振盪器  壓控振盪器  四相位振壓控振盪器  注入鎖定除頻器 
英文關鍵字 Low-power  multi-standard/multi-band  coexistence system  carrier generator  frequency synthesizer  transformer-feedback  transformer-coupled  current-reused  oscillator  voltage-controlled oscillator (VCO)  quadrature voltage-controlled oscillator (QVCO)  injection-locked frequency divider (ILFD) 
學科別分類
中文摘要 在多標準/多頻帶之多重輸出多重輸入的無線通訊系統中,主要透過射頻收發陣列的方式來增加資料傳輸速率和通道使用效率。然而收發陣列將導致增加晶片面積和功率消耗。為了能促使改善晶片面積的消耗,我們提出一個多標準/多頻帶共存接收機整合概念,用以實現電路功能方塊的最大重複使用。根據此共存整合概念,本論文提出兩個可以應用於2.4 – 2.5 GHz、5.1 – 5.9 GHz、3.1 – 10.6 GHz和57 – 64 GHz多標準/多頻帶之共存系統的頻率合成器架構,其將可適用於IEEE 802.11a/b/g/n/ac/ad WLANs和IEEE 802.15.3a/3c WPANs之標準規範。
本論文所提的兩個頻率合成器架構採用相同的頻率規劃(frequency planning),主要經由使用個別的再生式除頻電路去獲得關鍵載波頻率信號,其中兩個再生除頻電路分別由三個除二和二個除三電路與混頻器連接成一個閉迴路所組成。前者透過7,128 MHz輸入信號,則可以從第一級除二電路的輸入端獲得6,336 MHz載波信號。後者則為一個創新電路架構,其可從第一級除三電路的輸入端(由6,336 MHz輸入信號)產生7,128 MHz載波信號。因此,在應用 Mode-1和Mode-2 MB-OFDM超寬頻系統,僅需要一組鎖相迴路。除此之外,經由善用一顆寬可調範圍的四相位振盪器,結合需要的除頻器和混頻器,則可獲得5-GHz/2.4-GHz頻帶的載波信號。因此,相較於其它頻率合成器,本論文所提的頻率合成器架構具有較少電路需求的優勢。
本論文專注在所提的多標準/多頻帶頻率合成器之低功率高效能振盪器的設計與實現,全部有五個振盪器電路實現在0.18-μm RF CMOS製程中,其包含有一顆27-GHz和一顆7-GHz之差動壓控振盪器,兩顆7-GHz和一顆5.8-GHz之四相位壓控振盪器。其中本論文所提出的新式振盪器架構中主要包含有電流再利用(current reuse)和變壓器回授(transformer feedback)兩大關鍵技術,在低電壓和低功率操作條件之下具有低相位雜訊的優勢。
英文摘要 In the multi-standard/multi-band multiple-input multiple-output (MIMO) wireless communication systems, the use of radio-frequency (RF) transceiver-arrays topology enhances the data rate and the channel efficiency. While the systems with transceiver -arrays topology will cause the increases of chip area and power consumption. To further reduce the chip area, a multi-standard/multi-band coexistence receiver architecture is suggested to achieve the maximum reuses of function blocks. According to the above-mentioned concepts, two frequency synthesizer architectures are reported for the 2.4 – 2.5 GHz, 5.1 – 5.9 GHz, 3.1 – 10.6 GHz, and 57 – 64 GHz multi-standard/multi-band coexistence system in this dissertation. The reported frequency synthesizers are suitable for the IEEE 802.11a/b/g/n/ac/ad multi-standard wireless local area networks (WLANs) and 803.15.3a/3c wireless personal area networks (WPANs) applications.
The proposed two frequency synthesizer architectures are based on the same frequency planning to obtain key carrier-frequency signals by utilizing regenerative frequency dividers, in which one of the dividers is composed of three divide-by-two circuits and a mixer in a close-loop, and another is composed two divide-by-three circuits and a mixer. The former can obtain the 6,336 MHz carrier from the input node of the first divide-by-two stage via a 7,128 MHz input signal. The latter is a new idea we proposed in this dissertation, which generates the 7,128 MHz carrier (with a 6,336 MHz input signal) from the mixer output node. Therefore, only one phase-locked loop (PLL) is necessary for the Mode-1 and Mode-2 MB-OFDM UWB system operation. Besides, by making good use of a wide-tuning-range quadrature voltage-controlled oscillator (QVCO) combing with the necessary frequency dividers and mixers, the local oscillator (LO) signals can also be obtained for the conventional 5-GHz and 2.4-GHz bands. Thereby, the architectures of our reported frequency synthesizers have the integration advantages on that much fewer circuit blocks are required as compared to architectures reported.
This dissertation focuses on the design and implementation of low-power high-performance oscillators in the proposed multi-standard/multi-band frequency synthesizer. The completed design considerations of the related oscillators are presented. The proposed LC-tuned oscillators have been implemented in TSMC 0.18-μm RF CMOS technique, including a 27-GHz differential VCO, a 7-GHz differential VCO, two 7-GHz QVCOs, and a 5.8-GHz QVCO. The LC-tuned oscillators, which have the advantages of low-voltage and low-power operations with good phase noise performance, achieve the expected functions with current-reused and transformer-coupled feedback techniques.
論文目次 摘要……………………………………………………………………I
Abstract……………………………………………………………………..III
誌謝.................................................................................................................V
List of Tables……………………………………………………………......IX
List of Figures……………………………………………………………….X


1 Introduction……………………………………………………………..1

1.1 Motivation……………………………………………………………………1
1.2 Frequency Plan Proposal and Synthesizer Architectures………..………..5
1.2.1 Frequency Plan………………………………………………………….5
1.2.2 Synthesizer Architectures…………………………………………...…7
1.2.3 Novel Regenerative Frequency Divider……………………………….10
1.3 Thesis Organizations……………………………………………………….12

2 Differential LC VCO Design…………………………………………..14

2.1 Introduction………………………………………………………………...14
2.2 Non-linear Tail Current and Noise Up-conversion….................................16
2.3 LC VCO Design Considerations..........................…………………………18
2.3.1 Considerations of Phase Noise………………………………………...18
2.3.2 Considerations of Frequency Tuning Capacity………………………..19
2.3.3 Considerations of Tank Quality Factory……………………………….20
2.3.4 Fine Tune of the Cross-Coupled Pair………………………………….24
2.3.5 Considerations of the VCO bias circuit………………………………..26
2.4 27 GHz VCO Design………………………………………………..………27
2.5 Measurement Results………………………………………………………32
2.6 Summary…………………………………………………………………....35

3 Current-Reused Differential LC VCO Design……………………….37

3.1 Review of Current-Reused VCO…………...……………………………...37
3.2 Review of Transformer-Feedback VCO..………………………………....40
3.3 Current-Reused VCO Utilizing Trifilar-Transformer-Feedback………..42
3.3.1 Circuit Analysis………………………………………………………..42
3.3.2 LC-Tuned Tank Design………………………………………………..48
3.4 Experimental Results…………………………………………………….50
3.5 Summary……………………………………………………………………55

4 Transformer-Coupled QVCO Design…………...……………………56

4.1 Introduction………………………………………………………………...56
4.2 Review of QVCO Topology………………………………………………57
4.3 Review of Transformer-Coupled QVCO Topology……………………..60
4.4 Current-Reused QVCO Utilizing Transformer-Coupled Technique……61
4.4.1 CR-QVCO Design…………………………………………………...63
4.4.2 Experimental Results………………………………………………...64
4.5 Performance-Enhanced CR-QVCO…..…………………………………..68
4.5.1 Trifilar Transformer Design…………………………………………68
4.5.2 CR-QVCO Core Design……………………………………………..70
4.5.3 Experimental Results………………………………………………...71
4.6 Summary……………………………………………………………………73

5 Injection-Locked QVCO Design…...…………………………………75

5.1 Introduction………………………………………………………………...75
5.2 Injection-Locked QVCO…………………………………………………...75
5.2.1 Stacked Transformer-Feedback VCO………………………………….78
5.2.2 Stacked Transformer Design…………………………………………..81
5.2.3 Injected-Locked Frequency Divider…………………………………...86
5.2 Experimental Results…………………………………………………….88
5.3 Summary……………………………………………………………………94

6. Conclusion………………………………………………………………..96

6.1 Conclusion…………………..…..………………………………………….96
6.2 Future Work……………………..………………………………………….99

Appendix A. Broadband Transformer-Coupled QVCO Design……….101

A.1 Broadband Transformer-Coupled Complementary QVCO Design…..101
A.1.1 Transformer Design…………………………………………………102
A.1.2 Switched-Capacitor Array Design…………………………………..105
A.2 Experimental Results…………………………………………………….107

References…………………………………………………………………110

About the Author………………………………………………………….116
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