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系統識別號 U0026-2507201210091700
論文名稱(中文) 應用增進載子遷移率技術之金氧半場效電晶體之電特性研究
論文名稱(英文) Investigation of Electrical Characteristics in High Performance MOSFET Utilizing Mobility Enhancement Technology
校院名稱 成功大學
系所名稱(中) 微電子工程研究所碩博士班
系所名稱(英) Institute of Microelectronics
學年度 100
學期 2
出版年 101
研究生(中文) 黃博勤
研究生(英文) Po-Chin Huang
學號 q18961329
學位類別 博士
語文別 英文
論文頁數 163頁
口試委員 指導教授-張守進
指導教授-吳三連
召集委員-李清庭
口試委員-曾永華
口試委員-方炎坤
口試委員-劉致為
口試委員-藍文厚
口試委員-柯誌欣
口試委員-黃耀聰
中文關鍵字 載子遷移率增強技術  離子衝擊化  低頻雜訊  溫度依存性  矽鍺  應變矽技術  混合矽基板方向技術  金氧半場效電晶體 
英文關鍵字 Mobility enhancement technology  impact ionization  low-frequency (1/f ) noise  temperature dependence  SiGe  strained-Si technology  stress memorization technique (SMT)  hybrid orientation technology (HOT)  MOSFET 
學科別分類
中文摘要   隨著金氧半場效電晶體元件的持續微縮,載子遷移率對於元件效能扮演著舉輕重的角色。在維持摩爾定律(Moore’s Law)的情況下,為了持續針對元件進行微縮,並同時提升元件的效能,因此增進載子遷移率技術被引進並應用到現有的互補式金氧半場效電晶體製成當中。本論文即是針對應用增進載子遷移率技術之金氧半場效電晶體元件,其相關電特性進行研究、分析及探討。

  首先,我們針對通道中具有雙軸應力(biaxial strain)之n型應變矽(strained-Si)及p型應變矽鍺(strained-SiGe)金氧半場效電晶體元件,透過一連串量測離子衝擊化效率(impact ionization efficiency)與最大通道電場之間的關係實驗,驗證在n型應變矽及p型應變矽鍺金氧半場效電晶體元件之中,增強之離子衝擊化的物理機制主要皆歸因於能隙大小的變化。然而,在雙軸應變矽金氧半場效電晶體元件中,離子衝擊化效率的增加仍必須分別考量,在n型應變矽金氧半場效電晶體元件中,矽鍺虛擬基板(SiGe virtual substrate)上源汲極區域之深度的差異對通道電場的影響;在p型應變矽鍺金氧半場效電晶體元件,由於在矽鍺之中離子衝擊化的起始能量(threshold energy)與應力無關,因此電洞增加之平均自由路徑(mean free path)也是造成離子衝擊化增強的另一因素。

  接著,我們藉由在n型金氧半場效電晶體元件的製程當中,添增一道應變記憶技術(stress memorization technique),使得元件的通道中具有較大的單軸伸張應力,引致之導電帶能帶變化為元件帶來諸多好處,元件在閘極線寬縮小至40奈米時,除驅動電流的提升可達7.2%之外,閘極漏電流以及低頻雜訊亦可獲得改善;此外,當元件操作在高溫下時,驅動電流的衰退及閘極漏電流的增加皆獲得抑制,意味著單軸應變矽n型金氧半場效電晶體元件對溫度的變化有較低的敏感度,有利於操作在極高或極低溫的特殊環境中。

  最後,我們發現利用Amorphization/Templated Recrystallization (ATR) method製作之混合方向基板 (hybrid orientation substrate),在ATR method的過程之中,Si+離子佈植所造成,位於製作n型金氧半場效電晶體之(100)基板區域的末端範圍損毀(end-of-range damage)及末端範圍圈缺陷(end-of-range loops),可藉由延長高溫回火的時間來進一步消除,藉此完成之n型金氧半場效電晶體將可以得到較好的氧化層界面品質,同時不影響到製作於同一基板上(110)基板區域上之p型金氧半場效電晶體的各項電特性。
英文摘要 Because of the continuous MOSFET scaling, carrier mobility becomes the key for maintaining Moore’s Law and booting CMOS performance. In order to obtain high performance MOSFET, mobility enhancement technologies are introduced and applied into state-of-the-art transistor structures. In this dissertation, we explore the electrical characteristics in high performance MOSFET using mobility technology, including biaxial and uniaxial strained-Si technologies, and hybrid orientation technology (HOT).

First, we present the ion ionization efficiency (IIE) in biaxial strained-Si nMOSFETs and strained-SiGe pMOSFETs. As compared with bulk Si MOSFETs, the enhanced IIE in biaxial strained devices is attributed to the narrowing of band gap, i.e., a decrease in the threshold energy of II, taking account into the difference in source/drain junction depth in strained-Si nMOSFETs and increased mean free path of the hole in strained-SiGe pMOSFETs, respectively.

Then, we explore the DC and low-frequency (1/f ) noise characteristics in uniaxial tensile strained-Si nMOSFETs with SMT process operated at room- and high-temperatures. It can observe that an approximately 7.2% drive current enhancement, lower gate leakage current, and improved 1/f noise characteristic in strained-Si nMOSFETs simultaneously. As temperature increased, strained-Si nMOSFETs exhibit less sensitivity of electrical characteristics to temperature. These are ascribed to the SMT process-induced tensile is truly transmitted into channel. The band splitting between the low-energy two out-of-plane (Δ2) valleys and high-energy in-plane (Δ4) valleys increase, leading to the reduced carrier scattering, and electron with the averaged lighter in-plane and heavier out-of-plane effective mass.

Finally, we investigate the Si/SiO2 interface property of CMOS fabricated on hybrid orientation substrate with amorphization/templated recrystallization (ATR) method. Through physical and electrical analyses, it finds that ATR process-induced defects at the recrystallized (100) regions are further repaired by increasing defect-removal annealing time, resulting in the improvement of the Si/SiO2 interface of nMOSFETs. Besides, no effect on pMOSFETs fabricated on (110) regions are observed, meaning that modified ATR process can be adopted for fabricating the state-of-the-art CMOS on a HOT wafer.
論文目次 Chinese Abstract...........................................i
English Abstract.........................................iii
Acknowledgement (Chinese)..................................v
Special Acknowledgement..................................vii
Contents................................................viii
Figure Captions..........................................xii

Chapter 1 Introduction.....................................1
1.1 Background and Motivation..............................1
1.2 Organization of the Dissertation.......................4
Reference..................................................6

Chapter 2 Strained-Si Technology and Hybrid Orientation Technology................................................12
2.1 Biaxial Strained-Si Technology........................12
2.1.1 Properties of Si/Si1-xGex Epitaxial Layer...........12
2.1.2 Band Gap of SiGe Alloys.............................13
2.1.3 Effect of Biaxial Strain on Conduction Band.........14
2.1.4 Effect of Biaxial Strain on Valance Band............15
2.1.5 Strained-SiGe on Si: Type I Band Alignment..........15
2.1.6 Strained-Si on Si: Type II Band Alignment...........17
2.2 Uniaxial Strained-Si Technology.......................18
2.2.1 Physics of Strain Effects in CMOS Transistors.......18
2.2.2 Stress Memorization Technique.......................20
2.3 Hybrid Orientation Technology.........................21
Reference.................................................24

Chapter 3 Study of Impact Ionization in Biaxial Strained CMOSFETs..................................................43
3.1 Comprehensive Understanding of Impact Ionization Efficiency in Strained-Si nMOSFETs........................43
3.1.1 Introduction........................................43
3.1.2 Strained-Si nMOSFETs Device Fabrication and Structure.................................................44
3.1.3 Invesigation of Impact Ionization Efficiency in Strained-Si nMOSFETs......................................45
3.1.4 Strain Dependence of Impact Ionization Efficiency in Strained-Si nMOSFETs......................................49
3.1.5 Enhancement of Impact Ionization Efficiency in Short-Channel Strained-Si nMOSFETs..............................50
3.1.6 Summary.............................................52
3.2 Investigation of Impact Ionization Efficiency in Strained-SiGe pMOSFETs....................................53
3.2.1 Introduction........................................53
3.2.2 Strained-SiGe pMOSFETs Device Fabrication and Structure.................................................54
3.2.3 Enhanced Impact Ionization in Strained-SiGe pMOSFETs..................................................55
3.2.4 Summary.............................................57
Reference.................................................58

Chapter 4 Evaluation of Electrical Characteristics in Uniaxial Tensile Strained nMOSFETs Using Stress Memorization Technique (SMT)..............................89
4.1 Introduction..........................................89
4.2 SMT Process and Device Fabrication....................91
4.3 Results and Discussion................................91
4.3.1 Enhancement of DC Characteristic and Interface Property of SMT nMOSFETs..................................91
4.3.2 Temperature Dependence of DC Characteristics of SMT nMOSFETs..................................................94
4.3.3 Temperature Dependence of 1/f Noise Characteristics of SMT nMOSFETs...........................................95
4.4 Summary...............................................98
Reference................................................100

Chapter 5 Interface Properties of CMOS Fabricated on Hybrid Orientation Substrate....................................121
5.1 Introduction.........................................121
5.2 HOT Process and Device Fabrication...................123
5.3 Results and Discussion...............................124
5.3.1 Results of SEM and AFM for HOT Wafers..............124
5.3.2 DC Characteristics.................................124
5.3.3 Interface Properties...............................125
5.3.4 Physical Mechanism of 1/f Noise....................128
5.4 Summary..............................................129
Reference................................................131

Chapter 6 Conclusion and Future Prospect.................151
6.1 Conclusion...........................................151
6.2 Future Prospect......................................153
Reference................................................156

Appendix A: Author Resume................................158
Appendix B: Publication List.............................159
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Chapter 3
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Chapter 4
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Chapter 5
[5.1] M. Yang, E. Gusev, M. Ieong, O. Gluschenkov, D. Boyd, K. Chan, P. Kozlowski, C. D’Emic, R. Sicina, P. Jamison, and A. Chou, “Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO2 gate dielectrics,” IEEE Electron Device Lett., vol. 24, no. 5, pp. 339-341, May 2003.
[5.2] M. V. Fischetti, Z. Ren, P. M. Solomon, M. Yang, and K. Rim, “Six band k.p calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain and silicon thickness,” J. Appl. Phys., vol. 94, no. 2, pp. 1079-1095, Jul. 2003.
[5.3] L. Chang, M. Ieong, and M. Yang, “CMOS circuit performance enhancement by surface orientation optimization,” IEEE Trans. Electron Devices, vol. 51, no. 10, pp. 1621-1627, Oct. 2004.
[5.4] M. Yang, V. Chan, S. H. Ku, M. Ieong, L. Shi, K. K. Chan, C. S. Murthy, R. T. Mo, H. S. Yang, E. A. Lehnef, Y. Surprid, F. F. Jamin, P. Oldiges, Y. Zhang, B. N. To, J. R. Holt, S. E. Steen, M. P. Chudzik, D. M. Fried, K. Bemstein, H. Zhu, C. Y. Sung, J. A. Ott, D. C. Boyd, and N. Rovedo, “On the integration of CMOS with hybrid crystal orientations,” in Proc. Symp. VLSI Technol. Dig. Tech., 2004, pp. 160-161.
[5.5] M. Yang, K. Chan, A. Kumar, S.-H. Lo, J. Sleight, L. Chang, R. Rao, S. Bedell, A. Ray, J. Ott, J. Patel, C. D’Emic, J. Rubino, Y. Zhang, L. Shi, S. Steen, E. Sikorski, J. Newbury, R. Meyer, B. To, P. Kozlowski, W. Graham, S. Maurer, S. Medd, D. Canaperi, L. Deligianni, J. Tornello, G. Gibson, T. Dalton, M. Ieong, and G. Shahidi, “Silicon-on-insulator MOSFETs with hybrid crystal orientations,” in Proc. Symp. VLSI Technol. Dig. Tech., 2006, pp. 131-132.
[5.6] H. Yin, C.Y. Sung, H. Ng, K. L. Saenger, V. Chan, S. Crowder, R. Zhang, J. Li, J.A. Ott, G. Pfeiffer, R. Bendernagel, S.B. Ko, Z. Ren, X. Chen, G. Wang, J. Liu, K. Cheng, A. Mesfin, R. Kelly, V. Ku, Z.J. Luo, N. Rovedo, K. Fogel, D.K. Sadana, M. Khare, and G. Shahidi, “Direct Silicon Bonded (DSB) Substrate Solid Phase Epitaxy (SPE) Integration Scheme Study for High Performance Bulk CMOS,” in IEDM Tech. Dig., 2006, pp. 1-4.
[5.7] K. L. Saenger, J. P. de Souza, K. E. Fogel, J. A. Ott, A. Reznicek, C. Y. Sung, D. K. Sadana, and H. Yin, “Amorphization/templated recrystallization method for changing the orientation of singlecrystal silicon: An alternative approach to hybrid orientation substrates,” Appl. Phys. Lett., vol. 87, no. 22, pp. 221 911-1-221 911-3, Nov. 2005.
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[5.12] G. Groeseneken, H. E. Maes, N. Beltran, and R. F. De Keersmaecker, “A Reliable Approach to Charge-Pumping Measurements in MOS Transistors,“ IEEE Trans. Electron Devices, vol. 31, no. 1, pp. 42-53, Jan. 1984.
[5.13] L. K. J. Vandamme, and R. G. M. Penning de Vries, “Correlation between MOST 1/f noise and CCD transfer inefficiency,” Solid State Electron., vol. 28, no. 10, pp. 1049-1056, Oct. 1985.
[5.14] M. V. Haartman and M. Östling, Low-Frequency Noise in Advanced MOS Devices. Dordrecht, The Netherlands: Springer-Verlag, 2007, pp. 109-110.
[5.15] M. J. Prest, A. R. Bacon, D. J. F. Fulgoni, T. J. Grasby, E. H. C. Parker, T. E. Whall, and A. M. Waite, “Low-frequency noise mechanisms in Si and pseudomorphic SiGe p-channel field-effect transistors,” Appl. Phys. Lett., vol. 85, no. 24, pp. 6019-6021, Dec. 2004.
[5.16] M. von Haartman, B. G. Malm, P. -E. Hellström, M. Ö stling, T. J. Grasby, T. E. Whall, E. H. C. Parker, K. Lyutovich, M. Oehme, and E. Kasper, “Impact of strain and channel orientation on the low-frequency noise performance of Si n- and pMOSFETs,” Solid State Electron., vol. 51, no. 5, pp. 771-777, May 2007.
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[5.19] T. Ohguro, T. Nagano, M. Fujiwara, M. Takayanagi, T. Shimizu, H.S.Momose, S. Nakamura, and Y. Toyoshima, “A study of analog characteristics of CMOS with heavily nitrided NO oxynitrides,” in VLSI Symp. Tech. Dig., 2001, pp. 91-92.
[5.20] R. Jayaraman and C. G. Sodini, “A 1/f noise technique to extract the oxide trap density near the conduction band edge of silicon,” IEEE Trans. Electron Devices, vol. 36, no. 9, pp. 1773-1782, Sep. 1989.
[5.21] F. Crupi, P. Srinivasan, P. Magnone, E. Simoen, C. Pace, D. Misra, and C. Claeys, “Impact of the interfacial layer on the low-frequency noise (1/f) behavior of MOSFETs with advanced gate stacks,” IEEE Electron Device Lett., vol. 27, no. 8, pp. 688-691, Aug. 2006.

Chapter 6
[6.1] S. Takagi and M. Takenaka, “III-V/Ge CMOS technologies on Si platform,” in Proc. Symp. VLSI Technol. Dig. Tech., 2010, pp. 147-148.
[6.2] J. -W. Lee, B. H. Lee, H. Shin, B. -G. Park, Y. J. Park, and Jong-Ho Lee, “Comparison of Low-Frequency Noise in Channel and Gate-Induced Drain Leakage Currents of High-k nFETs,” IEEE Electron Device Lett., vol. 31, no. 10, pp. 1086-1088, Oct. 2010.
[6.3] E. Simoen, and C. Claeys, “Random Telegraph Signal: a local probe for single point defect studies in solid-state devices,” Mater. Sci. Eng. B, vol. 91-92, pp. 136-143, Apr. 2002.
[6.4] M. Yokoyama, S. H. Kim, R. Zhang, N. Taoka, Y. Urabe, T. Maeda, H. Takagi, T. Yasuda, H. Yamada, O. Ichikawa, N. Fukuhara, M. Hata, M. Sugiyama, Y. Nakano, M. Takenaka, and S. Takagi, “CMOS Integration of InGaAs nMOSFETs and Ge pMOSFETs with Self-Align Ni-Based Metal S/D using Direct Wafer Bonding,” in Proc. Symp. VLSI Technol. Dig. Tech., 2011, pp. 60-61.
[6.5] J. Oh, S. -H. Lee, K. -S. Min, J. Huang, B. G. Min, B. Sassman, K. Jeon, W. -Y. Loh, J. Barnett, I. Ok, C. -Y. Kang, C. Smith, “SiGe CMOS on (110) Channel Orientation with Mobility Boosters: Surface Orientation, Channel Directions, and Uniaxial Strain,” in Proc. Symp. VLSI Technol. Dig. Tech., 2010, pp. 39-40.
[6.6] R. Zhang, N. Taoka, P. -C. Huang, M. Takenaka and S. Takagi, “1-nm-thick EOT High Mobility Ge n- and p-MOSFETs with Ultrathin GeOx/Ge MOS Interfaces Fabricated by Plasma Post Oxidation,” in IEDM Tech. Dig., 2011, pp. 642-645.
[6.7] R. Chau, B. Doyle, J. Kavalieros, D. Barlage, A. Murthy, M. Doczy, R. Arghavani, and S. Datta., “Advanced Depleted-Substrate Transistors: Single-Gate, Double-Gate, and Tri-Gate,” International Conference on Solid-State Devices and Materials (SSDM), Nagoya, Japan, 2002, pp. 68-69.
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