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系統識別號 U0026-2408202019273200
論文名稱(中文) 共濺鍍法開發氧化矽鉿介電層與鈦摻雜氧化矽鋅錫通道於薄膜電晶體電性優化及可靠度改善之研究
論文名稱(英文) Enhanced Electrical Performance and Reliability of Ti-SZTO Thin-Film Transistors with Hf1-xSixO2 Gate Dielectrics Using Co-sputtering Technique
校院名稱 成功大學
系所名稱(中) 微電子工程研究所
系所名稱(英) Institute of Microelectronics
學年度 108
學期 2
出版年 109
研究生(中文) 林辰恩
研究生(英文) Chen-En Lin
學號 Q16071186
學位類別 碩士
語文別 中文
論文頁數 122頁
口試委員 指導教授-王水進
口試委員-柯榮明
口試委員-林吉聰
口試委員-吳建宏
口試委員-許渭州
中文關鍵字 矽摻雜  氧化鉿  鈦摻雜  氧化矽鋅錫  共濺鍍  薄膜電晶體 
英文關鍵字 Silicon doping  hafnium oxide  titanium doping  silicon zinc tin oxide  co-sputtering  thin film transistor 
學科別分類
中文摘要 本論文研究旨在利用共濺鍍法於氧化鉿(HfO2)摻雜適量矽(Si)元素作為介電層及於氧化矽鋅錫(SiZnSnO, SZTO)摻雜適量鈦(Ti)元素作為通道層,並藉由適化熱退火製程以降低介電薄膜及通道薄膜內部與其界面之缺陷,進行具優越電性與可靠度之下閘極Hf1-xSixO2介電層Ti-SZTO薄膜電晶體(Thin film transistors, TFTs)元件之開發研究。本論文研究內容主要分為「具Hf1-xSixO2介電層之SZTO TFTs製備與介電材料特性及元件電性分析」、「具Hf0.82Si0.18O2介電層之Ti-SZTO TFTs製備與通道材料特性及元件電性分析」與「具Hf1-xSixO2介電層之Ti-SZTO TFTs可靠度分析」等三大部分,茲依序分述如下:
第一部份於「具Hf1-xSixO2介電層之SZTO TFTs製備與介電材料特性及元件電性分析」之研究,旨在使用共濺鍍法於HfO2薄膜中進行Si元素摻雜比例之調變,以製備出具不同Si摻雜之Hf1-xSixO2介電層,並結合SZTO通道層以進行具下閘極Hf1-xSixO2介電層之SZTO TFTs研製;藉由Si-O具高鍵解離能(Binding dissociation energy, BDE)之特性修補介電薄膜內部之氧空缺以減少缺陷捕獲電荷,並降低薄膜表面粗糙度;同時藉由介電層與SZTO通道層擁有共同Si元素緩和二者界面之不匹配性,此外,亦利用適化退火製程進一步優化介電薄膜之晶體品質,有效抑制漏電流且進一步提升元件之閘極控制力。實驗結果顯示,於所製備Hf1-xSixO2/SZTO TFTs元件中,Si (18 at%)摻雜於HfO2之Hf0.82Si0.18O2介電層經O2環境下以600 °C進行10 min熱退火後所製備之SZTO TFT呈現出最佳之元件電性,包括較高之電流開關比(I_on/I_off為9.79×107)、較小之臨界電壓(V_TH為0.32 V)、較低之次臨界擺幅(SS為98 mV/dec)、較高之場效移動率(μ_FE為31.6 cm2/V∙s)與較少之界面缺陷密度(D_it為1.23×1012 cm-2eV-1)。
第二部分於「具Hf0.82Si0.18O2介電層之Ti-SZTO TFTs製備與通道材料特性及元件電性分析」之研究,旨在使用第一部分研究所製備最適化Hf0.82Si0.18O2介電層為基礎,結合以共濺鍍法於SZTO通道薄膜進行不同Ti摻雜量之Ti-SZTO通道層之研製。除了透過摻入適當比例之Ti元素外,亦利用適當熱退火製程,降低薄膜內部氧空缺與界面缺陷,提升電晶體之特性。實驗結果顯示,所製備Hf0.82Si0.18O2/Ti-SZTO TFTs元件中,Ti (2.5 at%)摻雜於SZTO之Ti(2.5%)-SZTO通道層經N2環境下以200 °C進行10 min熱退火後所製備之TFT呈現出最佳之元件電性,包括最高之I_on/I_off (2.78×108)、最小之V_TH (0.23 V)、最低之SS (87 mV/dec)、最高之μ_FE (36.8 cm2/V∙s)與最少之D_it (8.97×1011 cm-2eV-1)。
第三部分為本論文之核心研究,藉由可靠度分析探討Si摻入HfO2與Ti摻入SZTO之影響,評估其應用於TFTs下之改善幅度。於沿用前兩部分之最佳製程參數,將HfO2/SZTO、Hf0.82Si0.18O2/SZTO與Hf0.82Si0.18O2/Ti(2.5%)-SZTO TFTs分別命名為元件A、B與C,藉由上述三種不同材料結構元件探討Si元素摻入HfO2介電層與Ti元素摻入SZTO通道層對TFT可靠度之影響。實驗結果顯示,與元件A相比,元件C於各項目中均呈現較小之臨界電壓偏移量(∆V_TH);於遲滯效應下,∆V_TH從0.310 V改善至0.018 V (改善~94%)。於正負偏壓應力下,∆V_TH從0.642/-0.601 V改善至0.103/-0.096 V (改善~83%/84%)。於熱穩定性分析下,∆V_TH從-0.419 V改善至-0.105 V (改善~75%)。於負偏壓與白光照射下,∆V_TH從-0.569 V改善至-0.165 V (改善~71%),主要應可歸因於介電與通道薄膜品質及界面之提升。另外於閘極漏電分析下得知高低電場下主導之漏電機制分別為傅勒-諾得翰穿隧(Fowler–Nordheim tunneling, F-N)與陷阱輔助穿隧(Trap-assisted tunneling, TAT),並證實缺陷減少確實有助於抑制漏電流產生。
本論文成功以共濺鍍法製備Hf1-xSixO2介電層與Ti-SZTO通道層之TFTs,有效改善界面品質、漏電流、閘極控制力等電性與可靠度,預期本研究所研發具備高驅動力與低功耗之Hf1-xSixO2/Ti-SZTO材料系統將有助於未來平面顯示器之應用。
英文摘要 The purpose of this thesis is to incorporate appropriate amounts of silicon (Si) in HfO2 dielectric layer and titanium (Ti) in SiZnSnO (SZTO) channel layer using RF co-sputtering processes. In addition, post deposition annealing (PDA) was also used to reduce the excessive defects in the thin film and improve interface quality. Experimental results that Ti-SZTO thin film transistors (TFTs) with Hf1-xSixO2 dielectrics show superior electrical performance and reliability. The contents of this thesis is mainly divided into three major parts, including “Preparation of SZTO TFTs with Hf1-xSixO2 dielectric layer with analysis of dielectric material properties and device electrical characteristics,” “Preparation of Ti-SZTO TFTs with Hf0.82Si0.18O2 dielectric layer with analysis of channel material properties and device electrical characteristics,” and “Reliability analysis of Ti-SZTO TFTs with Hf1-xSixO2 dielectric layer.”
The first part is aims at the research of “Preparation of SZTO TFTs with Hf1-xSixO2 dielectric layer with analysis of dielectric material properties and device electrical characteristics,” which adjust the Si doping ratio in HfO2 to prepare the Hf1-xSixO2 dielectric layer with co-sputtering processes, and combine the SZTO channel layer for fabricating SZTO TFTs with a bottom Hf1-xSixO2 gate dielectric. Through the material analysis show that Si-O has high bind dissociation energy (BDE) to repair the oxygen vacancies inside the dielectric and reduce the surface roughness of the film, which is expected to reduce the defect trapping charge. Most importantly, due to dielectric and SZTO channel both has Si elements, so that can optimize the mismatch of the interface. Furthermore, the PDA of the device can promote the crystal quality of the dielectric to effectively suppress leakage current and further improve the gate control of the device. The experimental results show that Hf0.82Si0.18O2/SZTO TFT can exhibit the best device electrical characteristics among other types of TFTs after dielectric PDA at 600 °C for 10 min in O2 ambient, including a higher on/off current ratio (I_on/I_off) of 9.79×107, lower threshold voltage (V_TH) of 0.32 V, lower subthreshold swing (SS) of 98 mV/dec, higher field-effect mobility (μ_FE) of 31.6 cm2∙V-1∙s-1 and lower interface trapped density (D_it) of 1.12×1012 cm-2eV-1.
The second part is the research of “Preparation of Ti-SZTO TFTs with Hf0.82Si0.18O2 dielectric layer with analysis of channel material properties and device electrical characteristics,” the purpose is to used the best Hf0.82Si0.18O2 dielectric layer which complete at the first of research, and combine the Ti-SZTO channel layer in different Ti content by co-sputtering processes. In the research process, through doping an appropriate proportion of Ti element and PDA with sufficient thermal energy to reduce the oxygen vacancies and interface defects of the films, so that the electronic characteristics of the devices can be further optimized. The experimental results show that Hf0.82Si0.18O2/Ti(2.5%)SZTO TFT can exhibit the best device electrical characteristics among other types of TFTs after channel PDA at 200 °C for 10 min in N2 ambient, including the highest I_on/I_off of 2.78×108, the lowest V_TH of 0.23 V, the lowest SS of 87 mV/dec, the highest μ_FE of 36.8 cm2∙V-1∙s-1 and the lowest D_it of 8.97×1011 cm-2eV-1.
The third part is the core of the thesis, to further explore the benefits of the incorporation of Si in HfO2 dielectric and Ti in SZTO channel layer with stability analysis. In addition, employing the optimized process parameters obtained from the experimental studies in the first two parts, HfO2/SZTO, Hf0.82Si0.18O2/SZTO and Hf0.82Si0.18O2/Ti(2.5%)-SZTO TFTs, which are referred to devices A, B and C, respectively, were fabricated and compared. The influence of Si incorporation in the HfO2 dielectric layer and Ti in the SZTO channel layer on the reliability of TFTs was investigated. Experimental results show that, On compared with those of device A, device C exhibits a smaller threshold voltage shift (∆V_TH) in each stability test, after hysteresis effect that ∆V_TH decreases from 0.310 V to 0.018 V (~94% reduction), after PGBS 1000 s that ∆V_TH decreases from 0.642 V to 0.103 V (~83% reduction), after NGBS 1000s that ∆V_TH decreases from -0.601 V to -0.096 V (~84% reduction), after thermal test (378 K) 1000 s that ∆V_TH decreases from -0.419 V to -0.105 V (~75% reduction) and after NBIS that ∆V_TH decreases from -0.569 V to -0.165 V (~71% reduction), respectively. Mainly attribute to the improvement of dielectric and channel film quality and interface, In addition, according to gate leakage analysis, it suggests that the dominant leakage mechanisms under high and low electric fields could be Fowler–Nordheim tunneling (F-N) and trap-assisted tunneling (TAT) leakage, respectively.
Ti-SZTO TFTs with Hf1-xSixO2 gate dielectric have been successfully fabricated with co-sputtering processes, which effectively improving the interface quality, leakage current and gate control to enhance the electrical characteristics and stability of devices. It is expected that the proposed Ti-SZTO TFTs with Hf1-xSixO2 dielectrics after suitable post annealing, which have been demonstrated having improved electric performance, would be a very potential candidate for applications of advanced displays.
論文目次 目錄
第1章 緒論 1
1-1 平面顯示器產業發展概論 1
1-2 非晶型氧化物通道材料發展概論 4
1-3 高介電常數材料之採用考量 14
1-4 研究動機 21
第2章 研究理論背景 25
2-1 薄膜電晶體之操作原理與參數萃取 25
2-1-1 TFT通道全空乏理論 25
2-1-2 薄膜電晶體操作原理 27
2-1-3 薄膜電晶體基本參數 29
2-2 MOS結構介電層缺陷探討與優化 34
2-2-1 MOS結構介電層缺陷簡介 34
2-2-2 氧化矽鉿缺陷探討與優化 35
2-3 MOS結構通道層缺陷探討與優化 38
2-3-1 MOS結構通道層缺陷簡介 38
2-3-2 鈦摻雜於氧化矽鋅錫之缺陷探討與優化 39
2-4 可靠度分析理論 42
2-5 閘極漏電流機制探討 49
第3章 具Hf1-xSixO2介電層Ti-SZTO TFTs之製備流程 52
3-1 射頻共濺鍍與電子束蒸鍍製程簡介 53
3-1-1 射頻共濺鍍系統簡介 53
3-1-2 電子真空束蒸鍍系統簡介 54
3-2 Ti-SZTO通道層搭配Hf1-xSixO2介電層TFT製備方法 56
第4章 氧化矽鉿與鈦摻雜氧化矽鋅錫材料及電性分析 60
4-1 Hf1-xSixO2介電層之材料與電性分析 60
4-1-1 X射線光電子能譜(X-ray photoelectron spectroscopy, XPS)薄膜分析 60
4-1-2 二次離子質譜分析儀(Secondary ion mass spectrometer, SIMS)薄膜縱深分析 62
4-1-3 X射線繞射儀(X-ray diffraction, XRD)薄膜晶體結構分析 64
4-1-4 J-V電性分析 66
4-1-5 C-V量測分析 68
4-1-6 原子力顯微鏡(Atomic force microscope, AFM)薄膜分析 70
4-2 鈦摻雜氧化矽鋅錫材料與電性分析 72
4-2-1 XPS薄膜分析 72
4-2-2 XRD薄膜分析 74
4-2-3 霍爾量測 75
4-2-4 穿透率分析 77
第5章 薄膜電晶體電性與可靠度分析 79
5-1 具Hf1-xSixO2介電層SZTO TFTs之電性分析 80
5-1-1介電層未退火Hf1-xSixO2/SZTO TFTs之電性分析 80
5-1-2介電層熱退火Hf1-xSixO2/SZTO TFTs之電性分析 84
5-2 具Hf0.82Si0.18O2介電層Ti-SZTO TFTs之電性分析 87
5-2-1通道層未退火Hf0.82Si0.18O2/Ti-SZTO TFTs之電性分析 87
5-2-2通道層熱退火Hf0.88Si0.18O2/Ti-SZTO TFTs之電性分析 90
5-3 具Hf1-xSixO2介電層Ti-SZTO TFTs之可靠度分析 93
5-3-1 閘極漏電流機制分析 95
5-3-2 正、反掃遲滯分析 96
5-3-3 於室溫下正、負偏壓應力測試 98
5-3-4 熱可靠度測試 100
5-3-5 照光與負偏壓應力可靠度 102
第6章 結論與未來研究建議 106
6-1 結論 106
6-2 未來研究之建議 109
參考資料 111

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