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系統識別號 U0026-2408201820272500
論文名稱(中文) 電子系統層級之除錯系統設計與例外處理程序架構實現於CASLab-GPU
論文名稱(英文) Debug System for ESL Design and Trap Handler Architecture on CASLAB-GPU
校院名稱 成功大學
系所名稱(中) 電腦與通信工程研究所
系所名稱(英) Institute of Computer & Communication
學年度 106
學期 2
出版年 107
研究生(中文) 金育涵
研究生(英文) Yu-Han Chin
學號 Q36054138
學位類別 碩士
語文別 中文
論文頁數 78頁
口試委員 指導教授-陳中和
口試委員-邱瀝毅
口試委員-郭致宏
口試委員-朱元三
口試委員-蕭勝夫
中文關鍵字 虛擬平台  協同模擬  繪圖處理器  除錯器  硬體除錯 
英文關鍵字 Virtual Platform  Co-simualtion  GPGPU Simulation  Hardware Debugging  GDB 
學科別分類
中文摘要 現今晶片系統設計,隨著技術與製程提升變得日益複雜、開發耗時,而提出了ESL設計方案。在開發階段進行軟硬體協同模擬,讓開發者在初期平台上測試軟體,與硬體架構設計並行處理,提高效率。然而不論是軟、硬體開發者,在測試與驗證的過程中,若平台上沒有一個良好的除錯環境協助開發,將拖延開發時程,違背ESL設計理念。因此在開發前期的模擬平台上實現一個有效率的除錯系統是必要的。
除錯系統可分為兩塊子系統,一個是軟體除錯工具,另一個是硬體支援除錯功能。過去的除錯系統設計,多半於軟硬體協同模擬平台,針對功能、架構完整的CPU硬體進行建置;但若是開發階段中的繪圖處理器(GPU)架構上設置除錯系統,將面對兩個問題。第一為過去的除錯系統是針對CPU設計,不論是軟體除錯工具或硬體除錯模組,皆無法直接移植、沿用;第二個挑戰是在硬體架構尚未定案的平台上,同時開發、驗證硬體除錯模組,將面臨設計效率不佳,以及難以驗證其除錯功能。
本論文針對上述兩個問題提出了改良與新的解決方案,首先是軟體除錯工具,以GDB擴展功能,採用遠端除錯模式支援GPU除錯。其次是提出了利用SystemC內核模擬機制,以軟體技術取代硬體除錯模組實作,加速在ESL設計初期建置除錯系統。最後是在GPU硬體架構中,同步開發硬體除錯模組,使GPU具備執行例外狀況程序的能力,並在開發後期能銜接初期的除錯系統方案,讓GPU模擬平台在前後期開發,都能具備一套有效率的除錯系統。
英文摘要 Electronic System Level (ESL) design let developers fulfill hardware co-simulated with software in early design stage of SoC platform. In order to have an efficient design with testing, building a debug system on simulation platform is necessary. It can be divided into software tools and hardware support, two parts for debugging. However, for developing a GPU platform, these kinds of virtual platform prototype have no compatible debugging tools and the GPU hardware doesn’t have the mechanism to support software debug functions as well.
Accordingly, we propose a novel design in SystemC simulation platform to improve the problem as described above. For software debugging tools, we use remote debugging functions of GDB and extend them to support GPU hardware. For GPU hardware debugging support, we present two different trade-off soultions which are the debug system for ESL design and the trap handler architecture for GPU. The former achieves a hardware halted mechanism by using SystemC simulation kernel features while the latter is a real hardware architecture design to support debug system. The following are results of our debug system on CASLab-GPU simulation plaform. First, supporting the GDB remote debugging is needed. Then, the debug functions are satisfied with both software and hardware GPU developers by developing an efficient, low-cost hardware design in debug system for the early design stage. Finally, a trap handler architecture at warp-level context switch on CASLab-GPU is developed.
In conclusion, we use an innovative way to build the debug system including the software tools ad hardware modules design for CASLab-GPU and CPU co-simulation platform.
論文目次 摘要 I
SUMMARY II
誌謝 VIII
目錄 IX
表目錄 XI
圖目錄 XII
第1章 Introduction 1
1.1 Motivation 2
1.2 Contribution 3
1.3 Organization 3
第2章 Background and Related Works 4
2.1 Debug System 4
2.2 GNU Debugger (GDB) 7
2.2.1 Introduction to GDB 7
2.2.2 Remote Debugging 7
2.3 CUDA-GDB 9
2.3.1 Introduction to CUDA-GDB 9
2.3.2 GDB Extension 9
2.4 Hardware Support for Debugging 11
2.4.1 Intel CPU 11
2.5 Electronic System Level (ESL) Design 12
第3章 CASLab-GPU with GDB Support 13
3.1 Introduction to CASLab-GPUSim Platform 14
3.2 CASLab-GPUSim Runtime System 14
3.2.1 OpenCL Runtime 14
3.2.2 HSA Runtime 16
3.3 CASLab-GPU Architecture 16
3.4 CASLab-GDB 16
3.4.1 CASLab-GDB Extension 18
3.4.2 Gdbstub design 19
3.4.3 Remote Serial Protocol (RSP) design 21
第4章 Trap Handler Architecture on CASLab-GPUSim 26
4.1 Debug System for ESL Design 26
4.1.1 Introduction to SystemC Simulation Kernel 27
4.1.2 Methodology and Implementation 30
4.2 Trap Handler Architecture on CASLab-GPUSim 33
4.2.1 CASLab-GPU Hardware Implementation 35
4.2.2 Trap Handler Controller 38
第5章 Evaluation and Results 45
5.1 Simulation Environment 45
5.2 Experiment Evaluation 46
5.2.1 Debug System for ESL Design 47
5.2.2 Trap Handler Architecture 60
5.2.3 Profiling Tool 71
第6章 Conclusions and Future works 75
參考文獻 77
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