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系統識別號 U0026-2307201313171000
論文名稱(中文) 考量元件匹配性與可繞線性之類比積體電路擺置演算法
論文名稱(英文) Matching-Driven and Routing-Aware Placement Algorithms for Analog Integrated Circuits
校院名稱 成功大學
系所名稱(中) 電機工程學系碩博士班
系所名稱(英) Department of Electrical Engineering
學年度 101
學期 2
出版年 102
研究生(中文) 林城伍
研究生(英文) Cheng-Wu Lin
學號 N28951277
學位類別 博士
語文別 英文
論文頁數 135頁
口試委員 召集委員-陳竹一
口試委員-王朝欽
口試委員-許孟烈
口試委員-黃俊岳
口試委員-劉濱達
口試委員-李順裕
口試委員-何宗易
指導教授-張順志
共同指導教授-林家民
中文關鍵字 類比電路擺置  共質心擺置  電容陣列  可繞線性 
英文關鍵字 Analog placement  common-centroid placement  capacitor array  routability 
學科別分類
中文摘要 由於類比電路的敏感度強,因此有許多的設計考量,例如製程變異、寄生效應不匹配、繞線所衍生之訊號偶合等等,除了電路設計的本質之外,電路佈局的品質也會嚴重地影響到電路效能。由於不同應用的類比電路有不同的設計考量,我們難以用一種通用的方法來實現所有電路的佈局,過去文獻有非常多關於類比電路的擺置方法,其中大部分的方法是以最小化佈局面積與繞線總長度作為目標,但是將面積最小化的結果可能會產生一個過度密集的擺置,進而造成可繞線性問題。
在本論文中,所探討的類比電路擺置方法著重在兩個課題:電容擺置與可繞線性擺置。電容擺置是針對電容陣列來產生合適的共質心擺置,其中電容陣列是廣泛應用在切換式電容電路中的一個基本單元,我們提出了兩個方法來實現匹配性考量之電容擺置,第一個方法是利用模擬退火演算法,在同時考量多個擺置限制的情況下依然有優異的擺置結果,而第二個方法則是利用解析法來減少擺置所需花費的時間。另一方面,為了解決電路擺置結果所可能衍生之繞線問題,我們進一步考量對稱島的邊界條件,並提出一個可繞線性考量之擺置方法,先評估繞線的擁擠程度,再對擺置結果進行擴展以產生足夠的繞線空間,如此一來,在擺置階段就可以消除一些繞線問題。
實驗結果顯示,我們所提出的二個電容擺置方法與過去文獻相比較,皆能夠達到較好的匹配性以及較高的元件相關性。此外,所提出的可繞線性考量之擺置方法可以有效地降低繞線的擁擠程度,並且確保類比電路擺置所要求之對稱性質。
英文摘要 Analog circuits are sensitive to many factors such as process variation, parasitic mismatches, and routing-induced signal coupling. In addition to circuit sizing, layout generation has a great impact on circuit performance. Since different analog circuits have different trade-offs among various aspects, it is difficult to apply a unified layout implementation approach for all circuits. Many placement methods have been studied for analog circuits, and most of these works were devoted to the minimization of layout area and total wirelength. However, area minimization may generate an over compact placement and thus cause routability issue.
In this dissertation, the proposed analog placement methods focus on two subjects, capacitor placement and routability-driven placement. The capacitor placement is used to construct common-centroid placements for capacitor arrays, which are a common component in switched-capacitor circuits. We present two methods to achieve mismatch-aware capacitor placement. The first method uses the simulated annealing algorithm to obtain superior results under various placement constraints. The second method employs an analytical approach to accelerate the placement process. To deal with possible routing issues caused by placement, we further consider symmetry-island boundary constraint and introduce a routability-driven placement methodology to alleviate the routing effects during the placement phase. The proposed placement algorithm performs congestion estimation followed by placement expansion to accomplish sufficient routing space.
Experimental results show that both the proposed capacitor placement methods achieve lower oxide-gradient-induced mismatch and higher capacitance correlation than those of previous works. Moreover, the proposed routability-driven placement approach is effective to minimize routing congestion without breaking the symmetry property of analog placement.
論文目次 Abstract (Chinese) I
Abstract III
Acknowledgements (Chinese) V
List of Tables IX
List of Figures X
Chapter 1. Introduction 1
1.1 Analog Placement 1
1.1.1 Placement Constraints 2
1.1.2 Placement Approaches 4
1.1.3 Placement Representations 6
1.2 Beyond the Minimization of Layout Area and Total Wirelength 8
1.2.1 Application-Specific Placer 8
1.2.2 Routing Congestion 11
1.3 Overview of the Dissertation 12
1.3.1 Matching-Driven Capacitor Placement 12
1.3.2 Analytical Method for Fast Capacitor Placement 13
1.3.3 Routing-Aware Analog Placement 14
1.4 Organization of the Dissertation 15
Chapter 2. Matching-Driven Capacitor Placement 16
2.1 Motivation 16
2.2 Problem Formulation 20
2.2.1 Oxide Gradient Model 22
2.2.2 Spatial Correlation Model 23
2.3 Pair-Sequence Representation 24
2.3.1 Matrix to Pair Sequence Transformation 24
2.3.2 Pair Sequence to Matrix Transformation 26
2.4 Basic Unit-Capacitor Pairing 27
2.5 Extended Unit-Capacitor Pairing 30
2.5.1 Dummy Unit Capacitors 34
2.5.2 Adjacent Unit Capacitors 35
2.5.3 Pairing Procedure 36
2.6 Placement Algorithm 40
2.6.1 Overview of Placement Flow 40
2.6.2 Placement Initialization 42
2.6.3 Perturbation 44
2.6.4 Maintaining a Feasible Placement 45
2.6.5 Efficiency Improvements 48
2.7 Experimental Results 49
2.7.1 Arbitrary-Ratio Capacitor Arrays 50
2.7.2 Integer-Ratio Capacitor Arrays 51
2.7.3 Capacitor Arrays with Dummy Capacitors 54
Chapter 3. Analytical Method for Fast Capacitor Placement 57
3.1 Motivation 57
3.2 Placement Exploration 59
3.2.1 Linear (First-Order) Gradient Error 64
3.2.2 Quadratic (Second-Order) Gradient Error 65
3.2.3 High-Order Gradient Errors and Device Correlation 67
3.2.4 Routing Channel Width 68
3.3 Placement Facilitation 70
3.3.1 Representative Entries 71
3.3.2 Representative Unit Capacitors 72
3.4 Modeling of Placement Cost Function 74
3.4.1 Linear Gradient Error 75
3.4.2 Quadratic Gradient Error 75
3.4.3 Routing Channel Width 77
3.5 Placement Algorithm 79
3.5.1 Global Placement 79
3.5.2 Legalization 81
3.5.3 Post Optimization 82
3.6 Experimental Results 84
Chapter 4. Routing-Aware Analog Placement 90
4.1 Motivation 90
4.2 Preliminaries 94
4.2.1 Symmetry Island and ASF-B*-tree Representation 94
4.2.2 Hierarchical Placement and HB*-tree Representation 95
4.3 Symmetry-Island Boundary Constraint 96
4.3.1 Boundary Constraint in 1D Symmetry Island 97
4.3.2 Boundary Constraint in 2D Symmetry Island 100
4.3.3 Maintaining a Feasible Placement 102
4.4 Routability-Driven Placement Methodology 105
4.4.1 Problem Formulation 105
4.4.2 Overview of Placement Flow 106
4.4.3 Congestion Estimation and Placement Expansion 107
4.4.4 Dummy Node Insertion outside a Symmetry Group 110
4.4.5 Dummy Node Insertion in a Symmetry Group 113
4.4.6 Placement Algorithm 117
4.5 Experimental Results 119
Chapter 5. Concluding Remarks and Future Work 122
5.1 Concluding Remarks 122
5.2 Future Work 124
Bibliography 126
Publication List 133
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