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系統識別號 U0026-2208201314190600
論文名稱(中文) 針對可靠的針腳限制介電濕潤晶片之考量電壓的晶片層級設計
論文名稱(英文) Voltage-Aware Chip-Level Design for Reliability-driven Pin-Constrained EWOD chips
校院名稱 成功大學
系所名稱(中) 資訊工程學系碩博士班
系所名稱(英) Institute of Computer Science and Information Engineering
學年度 101
學期 2
出版年 102
研究生(中文) 葉昇翰
研究生(英文) Sheng-Han Yeh
學號 P76004601
學位類別 碩士
語文別 英文
論文頁數 42頁
口試委員 指導教授-何宗易
口試委員-莊坤達
口試委員-林英超
中文關鍵字 介電濕潤  數位微流體  繞線  滯留電荷 
英文關鍵字 EWOD  digital microfluidic  routing  reliability 
學科別分類
中文摘要 介電濕潤晶片現在已成為實現針腳限制生物晶片的重要技術,在介電濕潤晶片的設計流程中,晶片可靠度是一個相當重要的議題,可靠度會直接的影響到生物實驗的成敗。根據參考文獻,影響可靠度最主要的因素是滯留電荷的問題,滯留電荷的造成起因於使用太大的驅動電壓去驅動晶片上的電極。除此之外,為了符合針腳限制的設計,使用同一訊號源驅動多個電極是不可避免地,若沒有好好分配驅動電壓也會產生滯留電荷的問題。除了滯留電荷問題之外,繞線的問題也增加了晶片設計的複雜度。現今還沒有相關的研究同時探討繞線的問題以及滯留電荷的問題,這使得產生出來的晶片有較高的機會在運作中失敗,也有可能因為繞線的複雜度太高而無法完成設計。因此,我們在這篇論文中針對可靠的針腳限制生物晶片提出基於網路流的演算法,我們的方法不只能夠將滯留電荷的影響減到最少,還提供一個全面的繞線結果。實驗結果映證了我們的演算法是有效的且可行的。
英文摘要 Electrowetting-on-dielectric (EWOD) chips have become the most promising technology to realize pin-constrained digital microfluidic biochips (PDMFBs). In the design flow of EWOD chips, reliability is a critical challenge as it directly affects execution of bioassays. The major factor to degrade chip reliability is the trapped charge problem, which is induced by excessive applied voltage. Nevertheless, to comply with the pin constraint for PDMFBs, signal merging is inevitably involved, and thereby incurring trapped charges due to unawareness of applied voltage. Except for the trapped charge problem, wire routing to accomplish electrical connections increases the design complexity of pin-constrained EWOD chips. Unfortunately, no existing works tackle the problems of excessive applied voltage and wire routing, and thus the resultant chip will have more probabilities to fail during execution or can not be realized because of wire routing problem. In this thesis, we present a network-flow based algorithm for reliability-driven pin-constrained EWOD chips. Our algorithm not only minimizes the reliability problem induced by signal merging but also provides a comprehensive routing solution for EWOD chip-level designs. The experimental results demonstrate the effectiveness of proposed algorithm on real-life chips.
論文目次 List of Tables vii
List of Figures viii
Chapter 1. Introduction 1
1.1 Related works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Our contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 2. Preliminaries 8
2.1 Pin-Constrained Broadcast Electrode-Addressing . . . . . . . . . . 8
2.2 Trapped Charge Problem . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Driving Voltage Issue . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 EWOD Chip Routing . . . . . . . . . . . . . . . . . . . . . . . . . 14
Chapter 3. Algorithm 16
3.1 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 Voltage-Constrained Compatibility Graph . . . . . . . . . . . . . 18
3.3 Incremental Search Technique . . . . . . . . . . . . . . . . . . . . 19
3.4 Simultaneously Broadcast Addressing And Routing . . . . . . . . 21
3.4.1 Generating Initial Electrode Set . . . . . . . . . . . . . . . 26
3.4.2 Min-Cost Maximum-Flow Formulation . . . . . . . . . . . . 27
3.4.3 Reroute Technique . . . . . . . . . . . . . . . . . . . . . . . 29
Chapter 4. Experimental results 32
Chapter 5. Conclusions 38
Bibliography 39
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[2] K. Chakrabarty, "Towards fault-tolerant digital microfluidic lab-on-chip: defects, fault modeling, testing, and recon figuration," Proc. IEEE ICBCS, pp. 329-332, 2008.

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[6] R. B. Fair, "Digital microfluidics: is a true lab-on-a-chip possible?,"Microfluidics and Nanofluidics, vol. 3, no. 3, pp. 245-281, 2007.

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[12] Y. Y. Lin, R. D. Evans, E. Welch, B. N. Hsu, A. C. Madison, R. B. Fair, "Low voltage electrowetting-on-dielectric platform using multi-layer in-sulators," Sensor. Actuat. B-Chem. 150, pp. 465-470, 2010.

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[16] H. J. J. Verheijen and M. W. J. Prins, "Reversible electrowetting and trapping of charge: model and experiments," ACS J. Langmuir, no. 15, pp. 6616-6620, 1999.

[17] T. Yan and M. D. F. Wong, "A correct network flow model for escape routing," Proc. ACM/IEEE DAC, pp. 332-335, 2009.

[18] T. Xu and K. Chakrabarty, "Broadcast electrode-addressing for pin-constrained multi-functional digital microfluidic biochips," Proc. IEEE/ACM DAC, pp. 173-178, 2008.

[19] T. Xu and K. Chakrabarty, "Fault Modeling and Functional Test Methods for Digital Microfluidic Biochips," IEEE Transactions on Biomedical Circuits and Systems, vol. 3, no. 4,pp. 241-253, 2009.
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