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系統識別號 U0026-2208201306073100
論文名稱(中文) 基於逐漸趨近式類比數位轉換器之生醫感測伏安式恆電位儀
論文名稱(英文) A Voltammetry Potentiostat Based on a Successive-Approximation ADC for Biosensor Applications
校院名稱 成功大學
系所名稱(中) 電機工程學系碩博士班
系所名稱(英) Department of Electrical Engineering
學年度 101
學期 2
出版年 102
研究生(中文) 施尚亨
研究生(英文) Shang-Heng Shih
學號 n26004781
學位類別 碩士
語文別 英文
論文頁數 85頁
口試委員 指導教授-劉濱達
口試委員-魏嘉玲
口試委員-黃俊岳
口試委員-陳春僥
口試委員-丁信文
中文關鍵字 恆電位儀  電化學感測器  連續漸進式轉換器  類比至數位轉換器 
英文關鍵字 potentiostat  successive approximation register  analog-to-digital converter 
學科別分類
中文摘要 本論文提出一個適用於伏安式恆電位儀的感測電流機制,並實現其感測電流電路。藉由高使用效率特性的連續漸進式類比數位轉換器的結合及感測機制與取樣方式的改良,提供大動態電流範圍量測的能力。為企求低功率,電路主體以低壓方向設計。
本論文電路設計解析度為十位元,主要供應電壓為0.6 V。此感測電路以連續漸進式類比數位轉換器之電容矩陣與電流範圍偵測電路共用取樣電容,並以多段取樣多段輸出的概念增加大電流感測能力,同時藉由電流範圍偵測電路及時脈電路的控制來改變多段取樣的頻率,以完成多段取樣的機制。另一方面,為達到微小電流的取樣能力及改善開關的線性度,使用了電位轉移技巧,以改善取樣開關的線性度問題並同時抑制漏電流的問題以進一步達到微小電流的取樣能力。
本感測電路以TSMC 0.18-μm 1P6M CMOS製程來模擬設計,在訊號頻寬為50 kHz和供應電壓為0.6 V環境下,於佈局後模擬結果顯示電流感測範圍為5 fA ~ 2.1 µA,peak SNDR為60.03 dB,功率消耗為1.26 μW。此外,量測結果顯示peak SNDR亦達到56.28 dB。
英文摘要 This thesis presents a mechanism of sensing current for voltammetry potentiostat, and implements a sensing current circuit of potentiostat. By using a high efficient successive-approximation ADC and the improvements of sampling mechanisms, the wide dynamic range of sensing current capability can be obtained. To achieve the feature of low power, the circuit is designed with low supply voltage. In the thesis, the resolution is 10-bit and the main supply voltage is merely 0.6 V. The sampling capacitors of the circuit are shared between SAR ADC and current detector. Besides, current detector and clock generator control internal operation frequency with a proposed multi-sampling method for the enhancement of the current sensing range. Moreover, in order to improve the problem of sampling iota and the linearity of the sampling switch, a level shifting technique is used. The proposed sensing current circuit is implemented in TSMC 0.18-μm 1P6M CMOS technology. Under 50-kHz input signal bandwidth and 0.6-V power supply, the simulated peak SNDR achieves 60.03 dB with only 1.26-μW power consumption and the current sensing range is 5 fA to 2.1 µA. Besides, the measured peak SNDR achieves 56.28 dB.
論文目次 Abstract (Chinese) i
Abstract (English) iii
Acknowledgement v
Table of Contents vii
List of Figures ix
List of Tables xii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Organization of the Thesis 3
Chapter 2 Voltammetry Potentiostat 5
2.1 Fundamental Concepts of Potentiostat 5
2.2 Fundamental Concepts of Voltammetry 8
2.2.1 Cyclic voltammetry 10
2.2.2 Differential pulse voltammetry 11
2.3 Fundamental Concepts of Potentiostat Noise 13
Chapter 3 Fundamental Concepts of Analog-to-Digital Converter 17
3.1 Fundamental Concepts of ADC 17
3.1.1 Nyquist-rate conversion 18
3.1.2 Oversampling conversion 19
3.2 SAR ADC 21
3.3 The Non-ideal Effect of SAR ADC 23
3.4 Leakage Current 26
3.4.1 Stack transistor 28
3.4.2 Considerations of leakage current 28
Chapter 4 Circuit Implementation 31
4.1 The Concepts of the Proposed Circuit 31
4.2 Current Detector 38
4.2.1 Comparator 39
4.3 SAR ADC 40
4.3.1 Capacitor array 41
4.3.2 Comparator 42
4.3.3 SAR logic 44
4.4 Control Logic 47
4.5 Clock Generator 51
4.5.1 Non-overlap clock generator 53
4.5.2 Level shifter 53
4.6 Summary 54
Chapter 5 Experimental Results and Comparison 55
5.1 Simulation Results 55
5.1.1 Layout 56
5.1.2 Simulation results 58
5.1.3 Comparison and discussion 64
5.2 Measurement Results 66
5.2.1 Measurement environment 66
5.2.2 Measurement results and discussion 69
5.2.3 Verification of potentiostat system 73
Chapter 6 Conclusions and Future Work 75
6.1 Conclusions 75
6.2 Future Work 76
References 79
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