進階搜尋


下載電子全文  
系統識別號 U0026-2208201303122400
論文名稱(中文) 高速網路密碼處理器之資料流架構設計
論文名稱(英文) A Dataflow-based Cryptographic Processing Unit for High-Throughput IPsec Processors
校院名稱 成功大學
系所名稱(中) 電腦與通信工程研究所
系所名稱(英) Institute of Computer & Communication
學年度 101
學期 2
出版年 102
研究生(中文) 王振傑
研究生(英文) Chen-Chieh Wang
電子信箱 ccwang.jay@gmail.com
學號 Q38941145
學位類別 博士
語文別 英文
論文頁數 93頁
口試委員 指導教授-陳中和
召集委員-蕭勝夫
口試委員-許明華
口試委員-朱元三
口試委員-李維聰
口試委員-王永鐘
口試委員-陳培殷
口試委員-蘇文鈺
中文關鍵字 網際網路安全協定  密碼處理器  全系統網路模擬平台 
英文關鍵字 AES  cryptographic processing unit  ESL  HMAC  IPsec  SHA 
學科別分類
中文摘要 網際網路安全協定(IPsec)透過加解密及認證等密碼演算法來提供網路安全的服務。在IPv6中,IPsec被訂定為必須支援的功能。另外IPsec 也被廣泛地應用在虛擬私人網路(VPN)及存儲區域網路(SAN)。傳統一般用途的處理器無法滿足高速網路安全晶片的高性能需求,所以需要一個高效能的硬體密碼處理器來加速密碼演算法的計算。我們提出一個以資料流架構為基礎的密碼處理器,除了針對加解密及認證的硬體加速器進行最佳化之外,使用資料流架構來整合這些密碼硬體加速器可以動態地發掘出硬體加速器之間的資料運算平行度,以提升整體效能。另外我們提出一套新穎的多指標滑動視窗架構來提升密碼處理器內部緩衝儲存器的使用率,並減少封包資料的搬移次數。我們提出的密碼處理器可同時支援傳輸模式及通道模式的網路安全晶片。與先前研究的相互比較之下,我們提出的密碼處理器可以減少43% 的硬體成本,同時提升最高達37% 的效能增益。另外,我們設計一套全系統網路模擬平台來有效的開發及驗證複雜的網路安全晶片。該平台除了支援新興的ESL設計方法可以讓我們在系統層次進行系統架構的探勘之外,也提供了與真實的網路銜接在一起的環境,透過建立真實的網路連線的驗證方法,讓整個開發過程更有效率。我們設計的全系統網路模擬平台也可被用來開發其他網路的硬體設備,例如:網路卸載引擎(TOE)、路由器或交換器。
英文摘要 Internet Protocol Security (IPsec) is a protocol suite for securing IP communications. In IPsec cryptographic processing, the encryption, decryption, and authentication operations are critical factors affecting the overall performance. A specialized cryptographic processing unit to take the advantages of regularity and parallelism in the cryptographic algorithms is highly desirable for high speed network.
In this dissertation, we propose a dataflow-based crypto processor architecture that inherently makes the best use of the obtainable parallelism. We propose a novel architecture called Multi-Pointer Sliding Window (MPSW) to improve the utilization of FIFO buffers as well as to reduce the number of data movements. The proposed design reduces 43% area cost and provides a better performance up to 37% compared to previous work.
In order to design and verify the IPsec processor, we develop a full-system Network Virtual Platform (NetVP) to support ESL design methodology. Using the ESL system, we are able to explore the optimized performance and designs considering various architectural issues in the system level. In addition, the NetVP system provides an on-line verification capability to enable the designed target to communicate with a real network for system validation. The proposed full-system NetVP can also be applied to the development of other kinds of network accelerators, such as TOE, iSCSI, network router, and network switch.
論文目次 LIST OF TABLES VI
LIST OF FIGURES VII

CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 3
1.2 CONTRIBUTIONS 5
1.3 ORGANIZATION OF THE DISSERTATION 6
CHAPTER 2 BACKGROUND AND RELATED WORK 7
2.1 DESIGN METHODOLOGY FOR NETWORK-RELATED HARDWARE DEVICES 7
2.2 CRYPTOGRAPHIC ALGORITHMS 10
2.2.1 Advanced Encryption Standard (AES) 10
2.2.2 Secure Hash Algorithm (SHA) and HMAC 13
2.3 INTERNET PROTOCOL SECURITY (IPSEC) 16
CHAPTER 3 PROPOSED CRYPTOGRAPHIC CORES 21
3.1 ENCRYPTION/DECRYPTION UNIT (EDU) 21
3.1.1 Dataflow-based AES Core 21
3.1.2 Key Expansion Unit 23
3.1.3 S-box 25
3.2 AUTHENTICATION UNIT (AU) 25
3.2.1 Dataflow-based HMAC Core 25
3.2.2 Optimized SHA-1 Core 28
3.3 SUMMARY 29
CHAPTER 4 PROPOSED CRYPTOGRAPHIC PROCESSING UNIT 30
4.1 STREAMING FIFO ARCHITECTURE 32
4.2 MULTI-POINTER SLIDING WINDOW (MPSW) ARCHITECTURE 33
4.3 MPSW IMPLEMENTATION OF THE CRYPTOPU 36
4.4 SUMMARY 38
CHAPTER 5 DESIGN METHODOLOGY FOR IPSEC PROCESSOR 39
5.1 NETWORK VIRTUAL PLATFORM (NETVP) 39
5.1.1 Virtual Network Environment (vLAN and vMAC) 40
5.1.2 Virtual Host Environment (vHOST) 44
5.2 IPSEC DESIGN AND VERIFICATION FLOW 48
5.2.1 IPsec Golden Testbench 48
5.2.2 IPsec Untimed Functional Model 50
5.2.3 IPsec Timed Model 52
5.3 PERFORMANCE OF THE NETVP 55
5.4 SUMMARY 58
CHAPTER 6 EXPERIMENTAL RESULTS 59
6.1 PERFORMANCE METRIC 59
6.2 EXPERIMENTAL ENVIRONMENT 60
6.3 ARCHITECTURE EXPLORATION RESULTS 62
6.3.1 Encryption/Decryption Unit (EDU) 65
6.3.2 Authentication Unit (AU) 66
6.3.3 Streaming FIFO Architecture 68
6.3.4 MPSW Architecture 70
6.3.5 CryptoPU with Bus Model 72
6.4 IMPLEMENTATION RESULTS 75
6.4.1 Encryption/Decryption Unit (EDU) 76
6.4.2 Authentication Unit (AU) 77
6.4.3 MPSW architecture 78
6.4.4 Cryptographic Processing Unit (CryptoPU) 79
6.5 COMPARISONS 81
CHAPTER 7 CONCLUSIONS 85

REFERENCES 87
VITA 92
PUBLICATION LIST 93
參考文獻 [1] W. Stallings, Cryptography and Network Security: Principles and Practice, Fifth Edition, Prentice Hall, 2011.
[2] S. Kent and K. Seo, “Security Architecture for the Internet Protocol,” IETF Network Working Group, RFC 4301, Dec. 2005.
[3] S. Kent, “IP Authentication Header,” IETF Network Working Group, RFC 4302, Dec. 2005.
[4] S. Kent, “IP Encapsulating Security Payload (ESP),” IETF Network Working Group, RFC 4303, Dec. 2005.
[5] V. Manral, “Cryptographic Algorithm Implementation Requirements for Encapsulating Security Payload (ESP) and Authentication Header (AH),” IETF Network Working Group, RFC 4835, Apr. 2007.
[6] R. Friend, “Making the Gigabit IPsec VPN Architecture Secure,” Computer, vol. 37, no. 6, pp. 54–60, Jun. 2004.
[7] B. Bailey, G. Martin, and A. Piziali, ESL Design and Verification: A Prescription for Electronic System Level Methodology, Morgan Kaufmann/Elsevier, 2007.
[8] Platform Architect, Synopsys Inc., http://www.synopsys.com/
[9] SoC Designer, Carbon Design Systems Inc., http://www.carbondesignsystems.com/
[10] M.-Y. Wang and C.-W. Wu, “A Mesh-Structured Scalable IPsec Processor,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 5, pp. 725–731, May 2010.
[11] Open SystemC Initiative, “IEEE Std 1666-2011: SystemC Language Reference Manual,” IEEE Computer Society, Sept. 2011.
[12] Accellera Systems Initiative, http://www.accellera.org/
[13] L. Cai and D. Gajski, “Transaction Level Modeling: An Overview,” in Proc. International Conference on HW/SW Codesign and System Synthesis (CODES+ISSS), Oct. 2003, pp. 19–24.
[14] A. Haverinen, M. Leclercq, N. Weyrich, and D. Wingard, “SystemC based SoC Communication Modeling for the OCP Protocol,” OCP-IP, Oct. 2002.
[15] C.-C. Wang, R.-P. Wong, J.-W. Lin, and C.-H. Chen, “System-Level Development and Verification Framework for High-Performance System Accelerator,” in Proc. IEEE International Symposium on VLSI Design, Automation & Test (VLSI-DAT), Hsinchu, Taiwan, Apr. 27-30, 2009, pp. 359–362.
[16] J.-W. Lin, C.-C. Wang, C.-Y. Chang, C.-H. Chen, and K.-J. Lee, Y.-H. Chu, J.-C. Yeh, and Y.-C. Hsiao, “Full System Simulation and Verification Framework,” in Proc. Fifth International Conference on Information Assurance and Security (IAS), Xi'an, China, Aug. 18-20, 2009, pp. 165–168.
[17] J. Daemen and V. Rijmen, “AES Proposal: Rijndael,“ Mar. 1999.
[18] National Institute of Standards and Technology (NIST), MD, “FIPS 197, Advanced Encryption Standard (AES),” Nov. 2001.
[19] National Institute of Standards and Technology (NIST), MD, “SP-800-38A, Recommendation for Block Cipher Modes of Operation,” Dec. 2001.
[20] S. Morioka and A. Satoh, “A 10-Gbps Full-AES Crypto Design With a Twisted BDD S-Box Architecture,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 7, pp. 686–691, Jul. 2004.
[21] A. Rudra, P. K. Dubey, C. S. Jutla, V. Kumar, J. R. Rao, and P. Rohatgi, “Efficient Rijndael Encryption Implementation with Composite Field Arithmetic,” in Proc. CHES 2001, Lecture Notes Computer Science (LNCS), vol. 2162, 2001, pp. 171–184.
[22] A. Satoh, S. Morioka, K. Takano, and S. Munetoh, “A Compact Rijndael Hardware Architecture with S-Box Optimization,” in Proc. ASIACRYPT 2001, Lecture Notes Computer Science (LNCS), vol. 2248, 2001, pp. 239–254.
[23] X. Zhang and K. K. Parhi, “High-Speed VLSI Architectures for the AES Algorithm,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 9, pp. 957–967, Sept. 2004.
[24] A. Hodjat and I. Verbauwhede, “Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors,” IEEE Transactions on Computers, vol. 55, no. 4, pp. 366–372, Apr. 2006.
[25] S.-F. Hsiao, M.-C. Chen, and C.-S. Tu, “Memory-Free Low-Cost Designs of Advanced Encryption Standard Using Common Subexpression Elimination for Subfunctions in Transformations,” IEEE Transactions on Circuits and Systems – I: Regular Papers, vol. 53, no. 3, pp. 615–626, Mar. 2006.
[26] V. Fischer, M. Drutarovsky, P. Chodowiec, and F. Gramain, “InvMixColumn Decomposition and Multilevel Resource Sharing in AES Implementations,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 8, pp. 989–992, Aug. 2005.
[27] S. Mangard, M. Aigner, and S. Dominikus, “A Highly Regular and Scalable AES Hardware Architecture,” IEEE Transactions on Computers, vol. 52, no. 4, pp. 483–491, Apr. 2003.
[28] M-Y Wang, C-P Su, C-L Horng, C-W Wu, and C-T Huang, “Single- and Multi-core Configurable AES Architectures for Flexible Security,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 4, pp. 541–552, Apr. 2010.
[29] National Institute of Standards and Technology (NIST), MD, “FIPS 180-4, Secure Hash Standard (SHS),” Mar. 2012.
[30] H. Krawczyk, M. Bellare, and R. Canetti, “HMAC: Keyed-Hashing for Message Authentication,” IETF Network Working Group, RFC 2104, Feb. 1997.
[31] National Institute of Standards and Technology (NIST), MD, “FIPS 198-1, The Keyed-Hash Message Authentication Code (HMAC),” Jul. 2008.
[32] Y. K. Kang, D. W. Kim, T. W. Kwon, and J. R. Choi, “An Efficient Implementation of Hash Function Processor for IPsec,” in Proc. IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC), Taipei, Taiwan, Aug. 6–8, 2002, pp. 93–96.
[33] M.-Y. Wang, C.-P. Su, C.-T. Huang, and C.-W. Wu, “An HMAC Processor with Integrated SHA-1 and MD5 Algorithms,” in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, Jan. 27–30, 2004, pp. 456–458.
[34] E. Khan, M. W. El-Kharashi, F. Gebali, M. Abd-El-Barr, “Design and Performance Analysis of a Unified, Reconfigurable HMAC-Hash Unit,” IEEE Transactions on Circuits and Systems – I: Regular Papers, vol. 54, no. 12, pp. 2683–2695, Dec. 2007.
[35] H. E. Michail, A. P. Kakarountas,, A. S. Milidonis, and C. E. Goutis, “A Top-Down Design Methodology for Ultrahigh-Performance Hashing Cores,” IEEE Transactions on Dependable and Secure Computing, vol. 6, no. 4, pp. 255–268, Oct.-Dec. 2009.
[36] R. Chaves, G. Kuzmanov, L. Sousa, and S. Vassiliadis, “Cost-Efficient SHA Hardware Accelerators,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 8, pp. 999–1008, Aug. 2008.
[37] T. Kim, W. Jao, and S. Tjiang, “Arithmetic Optimization using Carry-Save-Adders,” in Proc. ACM/IEEE Design Automation Conference (DAC’98), 1998, pp. 433–438.
[38] QEMU, open source processor emulator, http://www.qemu.org/
[39] Simics, Wind River Systems Inc, http://www.windriver.com/products/simics/
[40] Wireshark, open source packet analyzer, http://www.wireshark.org/
[41] IPsec-Tools home page, http://ipsec-tools.sourceforge.net/
[42] P. Ezudheen, P. Chandran, J. Chandra, B. P. Simon, and D. Ravi, “Parallelizing SystemC Kernel for Fast Hardware Simulation on SMP Machines,” in Workshop on Principles of Advanced and Distributed Simulation, Jun. 2009, pp. 80–87.
[43] D. Yun, S. Kim, and S. Ha, “A Parallel Simulation Technique for Multicore Embedded Systems and Its Performance Analysis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. vol. 31, no. 1, pp. 121–131, Jan. 2012.
[44] Y. Nakamura, K. Hosokawa, I. Kuroda, K. Yoshikawa, and T. Yoshimura, “A Fast Hardware/Software Co-Verification Method for System-On-a-Chip by Using a C/C++ Simulator and FPGA Emulator with Shared Register Communication,” in Proc. ACM/IEEE Design Automation Conference (DAC), Jun. 2004, pp. 299–304.
[45] M. McLoone and J. V. McCanny, “A Single-Chip IPsec Cryptographic Processor,” in Proc. IEEE Workshop on Signal Processing Systems (SIPS), Oct. 16-18, 2002, pp. 133–138.
[46] C.-S. Ha, J. H. Lee, D. S. Leem, M.-S. Park, and B.-Y. Choi, “ASIC design of IPsec Hardware Accelerator for Network Security,” in Proc. IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC), Fukuoka, Japan, Aug. 2004, pp. 168–171.
[47] J. Lu and J. Lockwood, “IPsec Implementation on Xilinx Virtex-II Pro FPGA and Its Application,” in Proc. International Parallel and Distributed Processing Symposium (IPDPS), Apr. 2005.
[48] Y. Nishida, K. Kawai, K. Koike, K. Oyama, T. Hayashi, and H. Nouchi, “1 Gbit/s Bidirectional Full-wire Rate Communication LSI for Residential Gateways,” in Proc. IEEE Symposium on VLSI Circuits, Jun. 2007, pp. 138–139.
[49] M.-Y. Wang, “Scalable Architectures for Cryptographic Algorithms and Network Security Protocols,” PhD Dissertation, Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan, Jul. 2009.
[50] R. Cam and R. Tuck, “System Packet Interface Level 3: OC-48 System Interface for Physical and Link Layer Devices,” The Optical Internetworking Forum, Jun. 2000.
論文全文使用權限
  • 同意授權校內瀏覽/列印電子全文服務,於2015-08-27起公開。
  • 同意授權校外瀏覽/列印電子全文服務,於2015-08-27起公開。


  • 如您有疑問,請聯絡圖書館
    聯絡電話:(06)2757575#65773
    聯絡E-mail:etds@email.ncku.edu.tw