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系統識別號 U0026-2108201413443200
論文名稱(中文) 高頻率數位微流體生物晶片之考量可靠度晶片層級設計
論文名稱(英文) Reliability-Driven Chip-Level Design for High-Frequency Digital Microfluidic Biochips
校院名稱 成功大學
系所名稱(中) 資訊工程學系
系所名稱(英) Institute of Computer Science and Information Engineering
學年度 102
學期 2
出版年 103
研究生(中文) 余尚聰
研究生(英文) Shang-Tsung Yu
學號 P76011446
學位類別 碩士
語文別 英文
論文頁數 36頁
口試委員 指導教授-何宗易
口試委員-莊坤達
口試委員-林英超
中文關鍵字 介電濕潤  數位微流體  繞線  可靠度 
英文關鍵字 EWOD  digital microfluidic  routing  reliability 
學科別分類
中文摘要 介電濕潤晶片現在已成為實現針腳限制生物晶片的重要技術,隨著生化檢驗複雜度上升,針腳限制介電濕潤晶片的晶片層級設計廣泛地被使用,此設計包含了電極驅動訓號和繞線的規劃。此外,為了處理需要高速反應的生化檢驗,例如醫療上的快速篩檢,人們需要一個高頻率的介電濕潤晶片以達到高速反應的需求。 然而,根據參考文獻,當電極驅動與不驅動狀態的切換次數過高,將會使得電極與液珠之間接觸角變小,而此現象將會影響介電濕潤晶片的可靠度。 因此,在介電濕潤晶片的晶片層級設計中,晶片可靠度、驅動訊號分配、以及繞線問題需要同時考量。我們在這篇論文中針對可靠的針腳限制生物晶片層級設計提出基於網路流的演算法,藉著加入驅動切換次數的限制,電極的驅動切換次數可以有效的降低進而減少接觸角問題所帶來的影響。我們採用循序式地分配驅動訊號與繞線的演算法以克服複雜的繞線問題。實驗結果顯示,我們提出的方法有效率地降低接觸角問題。此外,我們所產生的晶片層級設計除了具有可靠度之外,也是一個可繞線的設計,而且符合指定的針腳限制。
英文摘要 Nowadays, electrowetting-on-dielectric (EWOD) chips have become the most popular actuator for droplet-based digital microfluidic biochips.
As the complexity of biochemical assay increases, the chip-level design of EWOD chips which integrates electrode addressing and wire routing are widely adopted.
Furthermore, to finish many time-sensitive bioassays such as incubation and emerging flash chemistry in a specific time, a high-frequency EWOD is used to satisfy the demand.
However, the reliability of the EWOD chip degrades due to the contact angle reduction problem incurred by huge number of switching times of an electrode.
Thus, the reliability issue, electrode addressing, and wire routing problem should be considered together in the chip-level design of an EWOD chips.
In this thesis, a graph-based chip-level design algorithm is presented.
By setting the switching-time constraint,
the number of switching times can be limited to minimize the impact of contact angle reductions problem.
Also, a progressive addressing and routing approach is proposed to overcome the challenge of complex wire routing problem.
Experimental results show that the influence of contact angle reduction problem can be effectively minimized by proposed algorithm.
A reliable chip-level design with feasible wire routing solution can be generated with number of pins are satisfied.
論文目次 List of Tables vii
List of Figures viii
Chapter 1. Introduction 1
1.0.1 Contributions.......................... 5
Chapter 2. Preliminaries 8
2.0.2 Pin-constrained Broadcast Addressing . . . . . . . . . . . . 8
2.0.3 ContactAngleReductionProblem . . . . . . . . . . . . . . 10
Chapter 3. Algorithm 14
3.0.4 ProblemFormulation ..................... 14
3.0.5 Switching-Time-Aware Actuation Refinement . . . . . . . . 17
3.0.6 IncrementalSearchTechnique................. 21
3.0.7 Switching-Time Constrained Compatibility Graph . . . . . 22
3.0.8 DecidetheSetofInitialPins ................. 22
3.0.9 MergePinsandElectrodes .................. 23
3.0.10 WireRoutingandEscapeRouting . . . . . . . . . . . . . . 25
Chapter 4. Experimental Results 28
Chapter 5. Conclusions 32
Bibliography 33
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