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系統識別號 U0026-2108201114291100
論文名稱(中文) 以ARM為基礎的多核心繪圖處理器架構
論文名稱(英文) An ARM-Based Many Core Architecture for 3D Graphic Processing
校院名稱 成功大學
系所名稱(中) 電腦與通信工程研究所
系所名稱(英) Institute of Computer & Communication
學年度 99
學期 2
出版年 100
研究生(中文) 虞先達
研究生(英文) Eric Shian-Da Yu
學號 q36984090
學位類別 碩士
語文別 中文
論文頁數 97頁
口試委員 指導教授-陳中和
口試委員-邱瀝毅
口試委員-李宗南
口試委員-蘇文鈺
中文關鍵字 ARM  多核心  軟硬體共同模擬  電子系統層級設計  砌塊式繪圖法 
英文關鍵字 ARM  many-core  software/hardware co-simulation  electronic system level design  tile-based rendering 
學科別分類
中文摘要 本論文提出一套適用於嵌入式系統的多核心3D繪圖處理器架構,以及針對此架構所設計的軟體繪圖管線、多核心程式編程模型,並對整個架構做性能分析。
本架構核心採用ARM處理器為基礎,並搭配向量處理單元,可以在高平行度運算下提供高性能的表現,並且比一般GPU提供了更高的編程彈性。而ARM處理器本身的快取與本地暫存,也讓ARM處理器可以高速存取本地資料。而繪圖任務分配也是採用純軟體架構,因此比起傳統GPU,軟體繪圖管線更能降低記憶體消耗、減少匯流排頻寬浪費、並增加運算平行度。
此外,我們對此架構設計了一套編程模型與函式庫,以QEMU-CoWare為模擬平台,讓開發者可以修改、變更軟體繪圖管線,或是用來做非繪圖運算的用途。而本論文最後也在此架構上,以OpenGL ES的標準為API,繪製3D模型,並與傳統的GPU進行效能上的比較。
英文摘要 This thesis presents a many-core 3D graphics processing architecture for embedded system together with its software rendering pipeline, programming model, and performance analysis.
The many-core architecture is ARM processor-based, and with a vector processing unit developed by this work. This vector unit provides higher performance and better programming flexibility than a regular GPU. The ARM processor with its own cache and local buffer allows high-speed accessing for the local data. The graphics tasks are allocated by a software task scheduler while the software graphics pipeline design can reduce memory consumption, bus bandwidth, and increase the operation parallelism.
In addition, we have also designed a programming model with libraries based on a QEMU-CoWare simulation platform, which allows developers to modify, change the software graphics pipeline or to be used for non-graphics processing. For the system, we implement various 3D models using the OpenGL ES as the standard API, and compare the performance with a traditional GPU.
論文目次 摘要 III
Abstract IV
誌謝 V
目錄 VI
表目錄 X
圖目錄 XI
第1章 序論 1
1.1 Motivation 1
1.2 Contribution 2
1.3 Organization 2
第2章 背景知識與相關研究 3
2.1 3D Computer Graphics 3
2.1.1 3D effects[20] 3
2.1.2 Rendering approaches 8
2.2 Graphics API standard 9
2.2.1 OpenGL 9
2.2.2 OpenGL ES[15][16][17] 10
2.3 3D Rendering Pipeline 12
2.3.1 Tile-based rendering 14
2.3.2 Tile-based versus traditional rendering 14
2.4 Full system simulation platform 16
2.4.1 Electronic System Level(ESL) 16
2.4.2 Platform Architect 16
2.4.3 QEMU 17
2.4.4 QEMU-CoWare Co-simulation[4] 18
2.5 Related work 19
2.5.1 Pixel-Planes 5[11] 19
2.5.2 Larrabee[12][13] 20
2.5.3 KAIST GPU[5][6][7] 22
2.5.4 3D Software rendering pipeline[29] 23
第3章 系統架構之設計與實現 26
3.1 Algorithm 27
3.1.1 Early Culling 27
3.1.2 Pixel Traversal 29
3.1.3 Clipping 35
3.2 Data flow 37
3.2.1 Multiple Buffering 38
3.3 Parallelism 42
3.3.1 Type of parallelism 42
3.3.2 Task scheduler 44
3.4 Data management 46
3.4.1 Packet transmission 46
3.4.2 Tile Number List 48
3.5 ARM Coprocessor 50
3.5.1 Basic architecture 50
3.5.2 Basic instruction 50
3.5.3 VFP 51
3.5.4 VGC 58
3.5.5 Result 62
3.6 Interrupt 63
3.6.1 New API (NAPI) 64
第4章 系統驗證架構之設計與實現 67
4.1 Execution time measurement 67
4.1.1 Native cycle capture 67
4.1.2 Ceiling/floor cycle capture 68
4.1.3 Cycle capture with time mask 70
4.2 Wrapper 73
4.2.1 System layers 73
4.2.2 Abstract hardware by wrappers 74
第5章 全系統模擬的驗證環境與實驗結果 77
5.1 Simulation platform 77
5.1.1 C model 77
5.1.2 QEMU-CoWare model 78
5.2 Verification 80
5.2.1 Verification methodology 81
5.2.2 Verification result 81
第6章 負載特性與數據分析 83
6.1 Computing power analysis 83
6.2 Workload characterization 84
6.3 Performance Comparison 86
6.3.1 GPU 2009[1][2][3] 86
6.3.2 3D Software rendering pipeline[29] 88
第7章 結論與未來展望 91
7.1 Conclusion 91
7.2 Future work 92
參考文獻 93
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