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系統識別號 U0026-2101202000131400
論文名稱(中文) 具十位元連續逼近式類比數位轉換器與交流偏移電壓校正之CMOS-MEMS電容式加速規後端處理電路
論文名稱(英文) Post-Processing Circuits for CMOS-MEMS Capacitive Accelerometer With 10-bit SAR ADC and AC Offset Calibration Technique
校院名稱 成功大學
系所名稱(中) 電機工程學系
系所名稱(英) Department of Electrical Engineering
學年度 108
學期 1
出版年 109
研究生(中文) 馮翼
研究生(英文) Yi Feng
學號 N26060185
學位類別 碩士
語文別 中文
論文頁數 137頁
口試委員 指導教授-魏嘉玲
口試委員-張順志
口試委員-蔡建泓
口試委員-鄭光偉
口試委員-黃崇勛
中文關鍵字 偏移電壓抑制  連續逼近式類比數位轉換器  電容式加速度感測器  全差分電容電橋  訊號處理電路 
英文關鍵字 Offset Cancellation Circuit  SAR ADC  Capacitive Accelerometer  Fully Differential Capacitive Bridge  Signal Processing Circuit 
學科別分類
中文摘要 近年來,隨著少子化問題日益嚴重與平均壽命不斷成長,未來將會面臨醫護人員嚴重不足的困境,因此穿戴式醫療裝置、遠端醫療等科技將能降低醫護人員的負擔。本論文將實現一單軸電容式加速度感測系統,應用於穿戴式裝置上,因此選用CMOS-MEMS製程來實現此系統,以達到小體積、低功耗及低成本之訴求。此外,由於感測器不匹配會導致交流偏移電壓,經過後端處理電路後,會轉為直流偏移,容易導致輸出飽和,因此提出了偏移消除迴路,來抑制交流偏移電壓以及直流偏移電壓。另外為了方便分析加速度訊號,因此使用了10位元之連續逼近式類比數位轉換器,將加速度訊號轉為數位碼。
本晶片採用台灣積體電路公司(TSMC) 0.35μm CMOS/MEMS 2P4M 3.3V混合訊號製程加上微機電後製程製作,選用48 S/B封裝,晶片總面積為2.834×2.201 mm2,包含感測器與訊號處理電路。由加速度振動量測平台(Shaker)提供穩定的加速度應力,可量測範圍為±14g,其靈敏度為218.4 (mV/g),全系統含感測器之總消耗功率為2.4mW。
英文摘要 Owing to the sub-replacement fertility and the growth of life expectancy recently, we will face the severe shortage of the medical personnel in the future. One of the solutions is to combine high technologies with medical industry, such as wearable devices and telemedicine, which can alleviate health care workers’ burdens. Therefore, this thesis adopted CMOS-MEMS process to implement the system due to its low size, low power and low cost. However, the mismatch between the MEMS sensor may induce ac offset which is converted into dc offset by post-processing circuits and makes the output signals saturate, so the offset cancellation loop is proposed to inhibit the offset voltage. The SAR ADC is implemented to convert the output signals to digital codes in order to analyze the acceleration signal easily.
The proposed chip, fabricated by Taiwan Semiconductor Manufacturing Company (TSMC) 0.35μm 2P4M mixed-signal standard CMOS process and MEMS post process, consists of the front-end sensor and the back-end signal processing circuits, and it occupies 2.834×2.201 mm2 area with 48 S/B package. The measured sensitivity is 218.4 (mV/g) within ±14g sensing range, and the power consumption is 2.4mW with a 3.3V power supply.
論文目次 第1章 簡介 1
1-1 研究動機 1
1-2 論文架構 2
第2章 文獻探討 3
2-1 加速度器感測技術 3
2-1-1 壓阻式感測 (Piezoresistive) 3
2-1-2 壓電式感測 (Piezoelectric) 4
2-1-3 熱感式感測 (Thermal) 4
2-1-4 電容式感測 (Capacitive) 4
2-2 電容式加速度器系統研究近況 6
2-2-1 電容式加速度器前端感測電路類型 6
2-2-2 製成變異導致電容不匹配之解決辦法 10
2-2-3 系統架構類型 14
2-2-4 省電技巧 16
2-3 類比數位轉換器類型 20
2-3-1 快閃式類比數位轉換器 (Flash ADC) 20
2-3-2 導管式類比數位轉換器 (Pipeline ADC) 21
2-3-3 連續逼近式類比數位轉換器 (Successive Approximation Register ADC, SAR ADC) 22
2-3-4 積分微分類比數位轉換器 (Sigma-Delta ADC) 23
第3章 系統架構與電路設計 25
3-1 系統介紹 25
3-2 CMOS-MEMS電容式加速度感測器 26
3-2-1 微機電製程介紹 26
3-2-2 電容式加速度感測器設計與模擬 27
3-3 全差分電容電橋(Fully Differential Capacitive Bridge) 29
3-4 降頻機制 33
3-5 電路設計與功能介紹 36
3-5-1 緩衝器(Buffer) 36
3-5-2 偏移消除迴路(Offset Cancellation Loop, OCL) 37
3-5-3 切換電容式低通濾波器(Switched-Capacitor Low Pass Filter) 46
3-5-4 可調式放大電路(Programmable Gain Amplifier, PGA)[11] 51
3-5-5 連續逼近式類比數位轉換器(SAR ADC) 52
3-5-6 時脈供應電路(Clock Supply Circuit) 61
3-5-7 共模迴路(Common Mode Feedback, CMFB) 65
第4章 模擬結果 68
4-1 電容式加速度感測器模擬 68
4-1-1 感測器加速度分析 68
4-1-2 感測器共振頻率分析 69
4-2 全差分電容電橋模擬 70
4-3 加速度感測器後端子電路模擬 72
4-3-1 緩衝器 72
4-3-2 偏移消除迴路(OCL) 73
4-3-3 切換電容式低通濾波器(SC LPF) 76
4-3-4 連續逼近式類比數位轉換器(SAR ADC) 79
4-3-5 時脈供應電路 88
4-4 全系統模擬 89
第5章 量測結果 90
5-1 量測環境與儀器 90
5-2 量測結果 93
5-2-1 微機電電容式加速度感測器 94
5-2-2 類比電路量測結果 96
5-2-3 混和訊號電路部分量測結果 102
5-2-4 全電路量測結果 103
5-2-5 規格比較表 107
第6章 結論與未來展望 109
參考文獻 111
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