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系統識別號 U0026-2008201914192100
論文名稱(中文) 高介電常數介電層與介面層應用於鍺基板鰭式/奈米線電晶體之研究
論文名稱(英文) Investigation of High-k Dielectric and Interface Layers on Ge Fin/NWFETs
校院名稱 成功大學
系所名稱(中) 微電子工程研究所
系所名稱(英) Institute of Microelectronics
學年度 107
學期 2
出版年 108
研究生(中文) 黃信富
研究生(英文) Hsin-Fu Huang
學號 Q16064032
學位類別 碩士
語文別 英文
論文頁數 67頁
口試委員 指導教授-王永和
口試委員-洪茂峰
口試委員-江德光
口試委員-李耀仁
口試委員-蘇俊榮
中文關鍵字   二氧化鉿  氨電漿  二氧化鍺  合成氣體快速退火  微波退火  鰭式電晶體  奈米線 
英文關鍵字 Germanium  HfO2  NH3 plasma  GeO2  microwave annealing  forming gas  FinFET  nanowire 
學科別分類
中文摘要 本論文研究以原子層沉積技術沉積高介電常數二氧化鉿製備低等效氧化層厚度金氧半電容器,隨著電晶體的微縮,為了持續改善元件的性能,傳統的矽基板顯然不足以持續摩爾定律,因此在基板的選擇上以高載子遷移率的鍺基板為研究對象,鍺的電子遷移率約為矽的兩倍,電洞遷移率約為矽的四倍,對於元件電流的提升有很大的幫助。另外,閘極氧化層隨著元件的微縮,厚度也越來越薄,伴隨的是增高的漏電流產生,因此高介電常數材料被用來取代傳統的二氧化矽介電層,但是鍺基板和高介電常數材料的介面中會有大量的介面陷阱,造成遷移率的劣化,因此需要有二氧化鍺當作其中的介面層以減緩介面陷阱的產生,然而二氧化鍺有不耐高溫還有容易分解成氧化鍺擴散到介電層,造成元件特性的下降,因此本論文提出了許多方式改善鍺通道元件所面臨的挑戰。
氮氧化鍺相對於二氧化鍺有更高的耐熱性和穩定度且不易裂解成氧化鍺,因此以氨電漿於二氧化鍺表面進行氨化,用以提升介面的熱穩定性以及減少穿隧電流的產生,接著以氧化鋁做為緩衝層,用以阻擋氧化鍺擴散造成缺陷的產生,最上層的介電層以二氧化鉿為主,目的是為了提高電容整體的介電常數以達成低等效氧化層厚度,整個閘極沉積皆在原子層沉積腔體裡進行,大大地減少外界條件的污染,經過適當的合成氣體快速退火或微波退火以修補介電層的缺陷,我們可得到等效氧化層厚度約為6.9Å,磁滯為60mV的低介面陷阱的金氧半電容器。
最後,我們將最佳的金氧半電容器條件應用於鍺基板鰭式和奈米線電晶體,於n型鰭式電晶體中,次臨界擺幅為64mv/dec,開關電流比為2x105;p型鰭式電晶體中,次臨界擺幅為99 mv/dec,開關電流比為5 x102,並將此鰭式電晶體成功應用於互補式金氧半反向器電路並成功製造出。在奈米線電晶體中,次臨界擺幅為73mv/dec,開關電流比為1.85x104。
英文摘要 In this thesis, we investigate the high-k dielectric and interface layer fabricated on Ge MOS capacitor. In order to continuously improve the performance of the devices with the scaling of Moore’s law, germanium is seemed as a best choice to replace traditional silicon substrate. The electron mobility of germanium is twice of silicon, and the hole mobility is four times of silicon. It is very helpful for the improvement of the driving currents. In addition, gate oxide becomes thinner and thinner, accompanied by the increasement of the leakage current. Therefore, the high dielectric constant (high-k) material is used to replace the conventional silicon dioxide dielectric layer. There are plenty interface traps between germanium and high-k dielectric degrading the mobility. Consequently, it is necessary to use GeO2 as the interface layer to decrease interface traps. However, GeO2 is not stable at high temperature and easily forms GeO diffusing into the dielectric layer. This research proposes several methods to improve the challenges of germanium.
Compared to GeO2, GeON has high thermal stability. Therefore, high quality GeO2 was grown on the Ge surface layer-by-layer, using NH3 plasma to enhance the thermal stability and uniformity. It is also confirmed that GeO2 is essential to passivate the Ge surface. Al2O3 was introduced as buffer layer to prevent HfO2 and GeO2 inter-mixing. The deposition of HfO2 is able to further scale down the EOT. All the gate stacks are deposited in ALD chamber. In this research, we developed HfO2/Al2O3/GeON/Ge gate stack with EOT of 6.9 Å, hysteresis of ~60 mV and low Dit.
Finally, we applied the high-k gate stacks on Ge FinFET and nanowire FET (NWFET). The electrical characteristics are studied in this thesis. We demonstrated subthreshold swing (S.S.) of 64mv/dec and Ion/Ioff ratio of 2x105 for n-FinFET. For p-FinFET, S.S. of 99mv/dec and Ion/Ioff ratio of 5x102 can be obtained. We successfully fabricated CMOS inverter by Ge FinFET in this reasearch. As for n-NWFET, we have S.S of 73mv/dec, Ion/Ioff ratio of 1.85x104.
論文目次 中文摘要 I
Abstract III
誌謝 V
Contents VI
Figure Captions VIII
Table Captions X
Chapter 1 Introduction 1
1.1 Background 1
1.1.1 High-k Metal Gate 5
1.1.2 Evolution of semiconductor structure 8
1.2 Motivation 10
1.2.1 Substrate choice - Germanium 10
1.2.2 GeO2 interfacial layer and nitridation 12
1.2.3 Buffer layer and high-k gate dielectric 17
1.2.4 Microwave annealing 19
1.3 Organization of the thesis 21
Chapter 2 Experimental Flow 23
2.1 MOS capacitor Fabrication 23
2.1.1 Implantation of backside wafer 23
2.1.2 Cleaning of wafer 23
2.1.3 Interfacial layer, buffer layer and high-k dielectric formation 23
2.1.4 Post metal annealing 24
2.2 Ge FinFET Fabrication 25
2.2.1 Ge epitaxy layer on silicon on insulator (SOI) 25
2.2.2 Cleaning of wafer 25
2.2.3 High-gate/metal gate formation 25
2.2.4 S/D implantation and activation 26
2.3 Ge NWFET Fabrication 29
2.3.1 Ge epitaxy layer on silicon on insulator (SOI) 29
2.3.2 Cleaning of wafer 29
2.3.3 High-gate/metal gate formation 29
Chapter 3 Results and Discussions 31
3.1 Electrical characteristics for Ge MOS CAP 31
3.1.1 GeO2 formation by H2O treatment 32
3.1.2 NH3 plasma on GeO2 interfacial layer 35
3.1.3 Annealing effect on Ge MOS CAP 38
3.1.4 Summary of Ge MOSCAP 43
3.2 TEM image of Ge MOSCAP 45
3.3 X-ray photoelectron spectroscopy (XPS) analysis 47
3.4 Electrical characteristic of Ge FinFET and NWFET 50
3.4.1 The extraction of subthreshold swing (S.S.) 50
3.4.2 Ion/Ioff ratio 51
3.4.3 Ge n- and p-FinFET 51
3.4.4 Ge n-NWFET 57
3.5 TEM image of Ge FinFET and NWFET 59
Chapter 4 Conclusion & Future Work 61
Reference 63
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