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系統識別號 U0026-2008201016510300
論文名稱(中文) 支援QEMU-CoWare平台之模擬同步分析器
論文名稱(英文) QEMU-CoWare Full System Simulation Platform with Simulation Synchronization Profiler
校院名稱 成功大學
系所名稱(中) 電腦與通信工程研究所
系所名稱(英) Institute of Computer & Communication
學年度 98
學期 2
出版年 99
研究生(中文) 陳冠仲
研究生(英文) Kuan-Chung Chen
學號 q3697420
學位類別 碩士
語文別 中文
論文頁數 81頁
口試委員 指導教授-陳中和
口試委員-謝錫堃
召集委員-黃穎聰
口試委員-邱瀝毅
中文關鍵字 電子系統層級設計  全系統模擬  軟硬體協同設計  軟硬體切割  軟硬體整合  效能分析 
英文關鍵字 electronic system level design  full system simulation  hardware-software co-desig  hardware-software partition  hardware-software integration  performance analysis 
學科別分類
中文摘要 本論文提出一套基於電子系統層級設計流程,在軟硬體切割後採用QEMUCoWare全系統設計與模擬之效能分析架構。由於在此模擬環境中軟硬體是以不同模擬程式與精確度進行模擬,所以只能驗證功能而無法做有效地軟硬體效能分析。然而應用程式、驅動程式與硬體之間的整合程度,往往對整個平台效能有很大的影響。因此我們建立了一個軟硬體同步效能分析的機制,讓使用者可以透過高速軟體模擬功能進行軟硬體協同設計之外,還可透過此同步機制完成軟硬體效能分析,透過分析結果可以推估應用程式驅動程式與硬體之間的合作情況,再由這些分析數據微調軟硬體配置,以期在平台開發初期就能達到極高的軟硬體整合程度。
我們以 ARM 嵌入式系統做為欲模擬的平台環境。透過QEMU 模擬的ARM系統來啟動Linux 作業系統,並且經由修改QEMU 的CPU 模擬器以達到軟體效能分析的效果。然而QEMU 是無時序概念的,因此無法從QEMU 中得到精確的執行週期,只能達到執行指令數精確,所以我們在QEMU 與CoWare 之間設計同步器,透過此同步器分別截取QEMU 所計算的軟體指令執行數與CoWare 內模擬硬體執行週期,提供使用者軟硬體執行相對時間以利實現效能分析。
英文摘要 In this thesis, we propose an architecture binding full system simulation and hardware-software synchronization profiling using QEMU and CoWare based on electronic system level design. We can use it not only to do hardware-software co-design but also to analyze the hardware-software integration which can affect the system performance greatly. Due to the different simulation accuracy and simulator between CoWare and QEMU in our full system simulation platform, we can hardly realize the timing information among CPU and other peripherals simulated in CoWare. In order to conquer this problem, we develop a synchronization method and apply it to full system
simulation. It can not only keep the simulation speed but also provide the simple timing information between CPU and the hardware under developing.
We use ARM embedded system as our simulation environment and design the synchronizer to fetch the timing information between the hardware modules modeled in CoWare and the software system run in QEMU. And then we can use the information to achieve synchronization profiling for performance evaluation of the specific hardware-software partition. We then can consider whether to redo the hardware-software partition according to the performance results.
論文目次 摘要 I
Abstract II
致謝 III
目錄 IV
圖目錄 VIII
表目錄 X
第1章 序論 1
1.1 研究動機 1
1.2 研究貢獻 2
1.3 論文編排 3
第2章 背景知識與相關研究 4
2.1 Hardware-Software Co-design 4
2.1.1 Electronic System Level Design 4
2.1.2 Hardware-Software Partition 10
2.2 Full system simulation platform 12
2.2.1 Simics: A Full System Simulation Platform 13
2.2.2 FacSim 16
2.2.3 QEMU-SystemC 16
2.2.4 QEMU-CoWare 17
2.3 CPU Instruction Set Simulator 21
2.3.1 Interpretive Simulation 22
2.3.2 Compiled Simulation 23
2.3.3 Dynamic Compiled Simulation 24
2.4 Virtual Machine Monitor inside QEMU 25
2.4.1 Processor Emulator 27
2.4.2 Peripheral Model 29
2.4.3 Interrupt Handler 29
2.5 Application Debugger and Profiler 30
2.5.1 GDB 30
2.5.2 Gprof 31
2.5.3 OProfile 32
2.5.4 Rerun 32
第3章 QEMU軟體指令分析器架構設計與實現 34
3.1 Problems of Hardware-Software Partition in Full System Simulation 34
3.2 QEMU Enhancement for ISS Profiler 37
3.2.1 Translation Block 38
3.2.2 QEMU Execution Flow 39
3.2.3 Software Profiler Architecture 43
3.3 Back-end Process for Software Profiling 45
3.3.1 Symbol Table 46
3.3.2 Back-end Profiler for Non-MMU OS Implementation 51
3.3.3 Back-end Profiler for Linux OS Implementation 52
3.4 Summary 53
第4章 軟硬體同步分析器之架構與實現 54
4.1 Problem Statement 54
4.2 Simulation Synchronization Profiler Architecture 56
4.3 Implementation on 3D Graphic Process Unit 59
4.3.1 Geometry Engine 60
4.3.2 Rasterizer Engine 61
4.3.3 DIBR Engine 62
4.4 Summary 63
第5章 實驗環境及實驗結果 64
5.1 Simulation Environment 64
5.2 Software Profiler Verification 65
5.3 Synchronization Profiler Verification 69
5.4 3D GPU Offload Engine Performance Evaluation 70
5.5 Summary 76
第6章 結論與未來展望 77
6.1 結論 77
6.2 未來展望 78
Reference 79
參考文獻 [1] A. Munshi and J.Leech, 「OpenGL ES Common/Common-Lite Profile Specification Version 1.1.10,」 Khronos Group, Apr. 2007.
[2] B. Fabrice, 「QEMU, a Fast and Portable Dynamic Translator,」 Proceeding of USENIX Annual Technical Conference, pp. 41-46, 2005.
[3] CoWare, ConvergenSC Training Manual rev:1Mar06, CoWare, Inc., 2006.
[4] D. C. Black and J. Donovan, 「SystemC from the Ground up,」 Kluwer Acadmic Publishers, 2004.
[5] D. Gajski and L. Cai, 「Transaction Level Modeling: An Overview,」 HW/SW Co-Design Conference (CODES), pp. 19-24, Oct. 2003.
[6] D. R. Hower and M. D. Hill, 「Rerun: Exploiting Episodes for Lightweight Memory Race Recording,」 in Proc. of the 35th Annual International Symposium on Computer Architecture (ISCA), June 2008.
[7] G. Schirner, A. Gerstlauer and R. Domer, 「Fast and Accurate Processor Models for Efficient MPSoC Design,」 ACM TODAES, vol. 15, Iss. 2, Article 10, Feb. 2010.
[8] GNU Project Debugger, http://www.gnu.org/software/gdb.
[9] GNU Profiler, http://www.cs.utah.edu/dept/old/texinfo/as/gprof.html.
[10] Imagination Technologies Ltd., 「POWERVR MBX OpenGL ES 1.x SDK,」 http://www.imgtec.com/powervr/insider/sdk/KhronosOpenGLES1xMBX.asp.
[11] M. Reshadi, P. Mishra, and N. Dutt, 「Instruction Set Compiled Simulation: A Technique for Fast and Flexible Instruction Set Simulation,」 in Proc. of IEEE/ACM 40th Design Automation Conference(DAC), Jun. 2003
[12] M. Reshadi and N Dutt, 「Reducing Compilation Time Overhead in Compiled Simultor,」 in Proc. of IEEE 21st International Conference on Computer Design(ICCD), Oct. 2003
[13] M. Reshadi, P. Mishra, and N. Dutt, 「Hybrid-Compiled Simulation: an Efficient Technique for Instruction-Set Architecture Simulation,」 ACM Tran. on Embedded Computing Systems(TECS), Vol. 8, No. 3, Apr. 2009
[14] M. R. Guthaus, J. S. Ringenberg and D. Ernst, 「MiBench: A free, commercially representative embedded benchmark suite,」 Proceedings of 2008 IEEE International Workshop on Workload Characterization (WWC』01), Austin, TX, USA, Dec 2001.
[15] OProfile, http://oprofile.sourceforge.net.
[16] P. S. Magnusson, M. Christensson, J. Eskilson, D. Forsgren, G. Hallberg, J. Hogberg, F. Larsson, A. Moestedt and B. Werner, 「Simics: A Full System Simulation Platform,」 IEEE Computer, vol. 35, Iss. 2, pp. 50-58, Feb. 2002.
[17] QEMU-SystemC, GreenSocs, http://www.greensocs.com/projects/QEMUSystemC.
[18] R. K. Gupta and G. D. Micheli, 「Hardware-software cosynthesis for digital systems,」 IEEE Design & Test of Computers, vol. 10, no. 3, pp. 29-41, Sept. 1993.
[19] R.-P. Wong, 「A QEMU-based Electronic System Level System Simulation Platform,」 Master thesis, Dept. of Electrical Engineering, National Cheng Kung University, 2008.
[20] S. Takaki, A. Masuda, H. Eichel, G. Otomo, T. Miyamori, K. Kohno and N. Matsumoto, 「Hardware/Software Partitioning Methodology for Systems on Chip(SoCs) with RISK Host and Configurable Microprocessors,」 http://www.design-reuse.com/articles/6978/hardware-software-partitioning-methodology-for-systems-on-chip-socs-with-risc-host-and-configurable-microprocessors.html .
[21] T. Austin et al., 「Simplescalar,」 http://www.simplescalar.com.
[22] T. Grotker, S. Liao, G. Martin, and S. Swan, 「System Design with SystemC,」 Kluwer Acadmic Publishers, 2002.
[23] WH Wolf, 「Hardware-software co-design of embedded systems,」 Proceeding of the IEEE, vol. 82, NO. 7, pp.967-989, July 1994.
[24] X.-Z. Shen, 「Full System Design and Simulation of a Multi-view Graphics Processor using QEMU,」 Master thesis, Dept. of Electrical Engineering, National Cheng Kung University, 2009.
[25] X.-Z. Shen, S.-Y. Lee, and C.-H. Chen, 「Full System Simulation with QEMU: an Approach to Multi-View 3D GPU Design,」 IEEE International Symposium on Circuits and Systems (ISCAS), May 30 - June 2, 2010, Paris, France.
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