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系統識別號 U0026-2001202021444900
論文名稱(中文) 全內建之低功耗低頻振盪器
論文名稱(英文) Fully Built-In Low-Power Low-Frequency Oscillator
校院名稱 成功大學
系所名稱(中) 電機工程學系
系所名稱(英) Department of Electrical Engineering
學年度 108
學期 1
出版年 109
研究生(中文) 吳則緯
研究生(英文) Tse-Wei Wu
學號 N26050164
學位類別 碩士
語文別 中文
論文頁數 75頁
口試委員 指導教授-魏嘉玲
口試委員-蔡建泓
口試委員-張順志
口試委員-鄭光偉
口試委員-黃崇勛
中文關鍵字 全內建  低頻振盪器 
英文關鍵字 Low power consumption  Low frequency 
學科別分類
中文摘要 隨著生醫、物聯網等產業近期迅速發展,無線通訊的接收、運算和輸出等眾多功能都要集中於同一晶片上,當製程越來越進步且功能越來越豐富,功耗和裝置本身的大小越來越重要。為了降低總功耗,讓系統處在待機或深度休眠模式會是比較有效率的方法,於必要時再喚醒系統執行任務,因此本研究將利用虛擬電阻(Pseudo-resistor)降低充電電流,設計一個全內建、面積小的低功耗低頻振盪器。
本研究使用台灣積體電路公司(TSMC)提供之0.18μm 1P6M Mixed-signal Standard CMOS製程,晶片總面積為0.968×0.838mm^2,並採用DIP 28 S/B進行封裝,晶片有四個版本的低頻振盪器,包含偏壓電路、充放電電路和比較邏輯電路,且不需要off-chip被動元件,各版本面積分別為0.083mm^2、0.0098mm^2、0.046mm^2、0.053mm^2,四個版本post-sim皆可輸出1Hz的方波,但量測結果不佳,最低頻率只有350Hz左右。
英文摘要 Low power consumption is important to wireless communication system. To reduce the power consumption, we can make the system stay in sleep-mode, and send a signal to wake it up and back to operation-mode. This thesis propose a fully built-in, low power consumption, and low frequency oscillator which meets the requirements. The output frequency of all versions are designed at 1Hz, and three of them are tunable frequency.
The proposed chip is fabricated by TSMC 0.18μm 1P6M mixed-signal standard CMOS process, and the chip area is 0.811 mm2. This chip includes four versions of low-frequency oscillator. The oscillator consists of three parts: bias circuit, charging-discharging circuit, and comparison logic circuit. Each version’s core area is 0.083mm^2, 0.0098mm^2, 0.046mm^2, and 0.053mm^2. The off-chip passive components are needless. The output frequency of all versions are 1Hz in the post-simulation. But the measurement result isn’t good, the lowest frequency is stable at around 355Hz under the same conditions.
論文目次 第1章 簡介 1
1.1 研究動機 1
1.2 論文架構 2
第2章 文獻探討 3
2.1 背景知識 3
2.2 弛張振盪器研究近況 4
第3章 系統架構與電路設計 10
3.1 系統架構簡介 10
3.2 電路設計與功能介紹 10
3.2.1 全系統Version 1 10
3.2.2 全系統Version 2 20
3.2.3 全系統Version 3 27
3.2.4 全系統Version 4 28
第4章 模擬結果與佈局考量 30
4.1 模擬結果 30
4.1.1 子電路模擬 30
4.1.2 全系統模擬 32
4.2 佈局考量 41
4.3 打線圖 43
第5章 量測結果 45
5.1 量測環境與考量 45
5.2 量測結果與討論 47
5.3 規格與效能比較表 56
第6章 結論與未來展望 58
參考文獻 59

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