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系統識別號 U0026-1908202017310000
論文名稱(中文) 交叉式電阻式記憶體陣列應用於電子突觸之研究
論文名稱(英文) Development of Crossbar Resistive Random Access Memory Array for Synaptic Device Applications
校院名稱 成功大學
系所名稱(中) 微電子工程研究所
系所名稱(英) Institute of Microelectronics
學年度 108
學期 2
出版年 109
研究生(中文) 翁禹詮
研究生(英文) Yu-Chuan Weng
學號 Q16074231
學位類別 碩士
語文別 英文
論文頁數 126頁
口試委員 指導教授-王永和
口試委員-洪茂峰
口試委員-周德威
口試委員-李耀仁
口試委員-張鼎張
中文關鍵字 電阻式記憶體  電子突觸  突觸可塑性  原子層沉積氧化鉿  表面氬電漿處理 
英文關鍵字 RRAM  Electrical synapse  Synaptic plasticity  ALD HfO2  Argon plasma treatment 
學科別分類
中文摘要 近年來,隨著物聯網的蓬勃發展,越來越多的科學家投入類神經網路架構的研究,而其中高密度、低功耗的類神經網路架構一直是一個待解的議題。因此,具備突觸特性的電阻式記憶體相關研究便越來越受到關注。
此篇研究將使用原子層沉積法製備的氧化鉿薄膜作為介電層材料,開發適合做為電子突觸的記憶體陣列。本篇研究的重點將放在提升元件權重可塑性的線性精準度,藉由調整寫入的波形,元件可以保持約50個記憶阻態以及104的操作次數,並且擁有約0.39的非線性表現。
除此之外,我們也導入氬電漿製程,針對氧化鉿薄膜進行表面處理,藉由改變表面的粗糙度來增加元件的突觸特性以及電性表現。經過表面處理後的元件,操作電壓有明顯的降低,且元件的操作次數也有超過100倍以上的進步,而元件阻態的非線性度也從原本的0.39下降至0.06,非常接近完全的線性。
英文摘要 Recently, demand for IoT has increased rapidly. Therefore, many scientists have invested into the research of neuromorphic networks. However, how to achieve a high density and low-power neural network architecture remains a challenge. Consequently, resistive switching memory (RRAM) has attracted considerable attention because of its synaptic characteristics.
In this work, we use ALD deposited HfO2 as an RS layer to develop electrical synapses. Our research focuses on improving linearity accuracy and synaptic weight. By adjusting the input waveforms, about 50 memory states, 104 switching cycles, and 0.39 nonlinearity can be observed.
In addition, we applied an argon plasma treatment on the surface of HfO2 film. By increasing surface roughness it is possible to improve the electrical and synapse characteristics. After the plasma treatment, the program voltage decreased notably, the switching cycles show 100 times improvement, and the nonlinearity decreases to 0.06, which is very close to the ideal linearity.
論文目次 摘要 I
Abstract III
誌謝 V
Contents VII
List of Figures XII
List of Tables XX
Chapter 1 Introduction 1
1.1 Resistive Random-Access Memory 1
1.1.1 Background 1
1.1.2 Fundamental definitions 2
1.1.3 Conduction mechanisms 4
1.1.3.1 Ohmic conduction 4
1.1.3.2 Schottky emission 5
1.1.3.3 Poole-Frenkel emission 6
1.1.3.4 Tunneling 8
1.1.3.5 Hopping conduction 10
1.1.3.6 Space Charge Limited Current 11
1.1.4 Crossbar RRAM Array 13
1.1.4.1 Two-dimensional Crossbar Array 13
1.1.4.2 Three-dimensional Crossbar Array 16
1.2 Neuromorphic System 19
1.2.1 Background 19
1.2.2 Neuromorphic Computing 22
1.2.3 Synaptic Devices 24
1.2.4 Potentiation and Depression 26
1.2.5 Spike-Timing-Dependent Plasticity 28
1.3 Motivation 31
1.4 Organization of the Thesis 34
Chapter 2 Experiment 35
2.1 Fabrication Equipment 35
2.1.1 Mask Aligner 35
2.1.2 Spin Coater 36
2.1.3 Oven 36
2.1.4 Radio Frequency Sputtering (RF Sputtering) 37
2.1.5 Electron Beam Evaporator 39
2.1.6 Reactive Ion Etching system (RIE) 40
2.1.7 Atomic Layer Deposition system (ALD) 41
2.2 Material Analysis Equipment 42
2.2.1 Atomic Force Microscopy (AFM) 42
2.2.2 Energy-Dispersive X-ray Spectroscopy (EDS) 43
2.2.3 Focused Ion Beam (FIB) 44
2.2.4 Transmission Electron Microscopy (TEM) 45
2.3 Electrical Analysis Equipment 47
2.3.1 Agilent B1500A 47
2.4 Mask Layout Design 48
2.4.1 Mask Design 48
2.4.2 Pattern Design 49
2.5 Fabrication Processes 52
2.5.1 Substrate cleaning 52
2.5.2 Bottom Electrode 53
2.5.2.1 Lithography 53
2.5.2.2 RF Sputtering 54
2.5.2.3 Lift-off 55
2.5.3 Isolation Layer 55
2.5.4 Via Hole 56
2.5.4.1 Lithography 56
2.5.4.2 RIE Etching 57
2.5.5 Resistive Switching Layer 58
2.5.6 Plasma Treatment 58
2.5.7 Bottom Electrode Pad 59
2.5.7.1 Lithography 59
2.5.7.2 RIE Etching 60
2.5.8 Top Electrode 60
2.5.8.1 Lithography 60
2.5.8.2 RF Sputtering 62
2.5.8.3 Lift-off 62
2.5.9 Schematic of Workflow 64
Chapter 3 Results and Discussion 66
3.1 Pristine device Without APT 66
3.1.1 Physical Properties 66
3.1.1.1 TEM image of Device Cross-section 66
3.1.1.2 Energy Dispersive Spectroscopy of Elements Analysis 67
3.1.2 Electrical Properties 68
3.1.2.1 DC IV Characteristics 68
3.1.2.2 Curve Fitting (Conduction mechanism analysis) 70
3.1.2.3 Multi-level storage 72
3.1.2.4 Endurance 74
3.1.2.5 Data Retention 76
3.1.2.6 Cumulative Probability 77
3.1.2.7 Synaptic Characteristics 79
3.2 Argon Plasma Treatment (APT) 84
3.3 Device with APT 86
3.3.1 Physical Properties 86
3.3.1.1 TEM image of Device Cross-section 86
3.3.1.2 Energy Dispersive Spectroscopy of Elements Analysis 87
3.3.2 Electrical properties 88
3.3.2.1 DC IV Characteristics 88
3.3.2.2 Curve Fitting (Conduction mechanism analysis) 90
3.3.2.3 Multi-level storage 92
3.3.2.4 Endurance 94
3.3.2.5 Data Retention 96
3.3.2.6 Cumulative Probability 97
3.3.2.7 Synaptic Characteristics 99
3.4 Comparison between Pristine and Plasma Treated Devices 104
3.5 3x3 Crossbar RRAM Array 108
Chapter 4 Conclusion 112
Chapter 5 Future Works 114
References 116
參考文獻 [1] F. Yoshihisa, “Current Status of Nonvolatile Semiconductor Memory Technology.” Jpn. J. Appl. Phys., vol. 49, pp. 100001, Dec. 2010.
[2] S. Yu, B. Lee, and H.S. Wong “Metal oxide resistive switching memory, in Functional Metal Oxide Nanostructures,” New York: Springer-Verlag, pp. 316-317, 2011.
[3] H.S. Wong, H.Y. Lee, S. Yu, Y.S. Chen, Y. Wu, P.S. Chen, B. Lee, F.T. Chen, and M.J. Tsai, “Metal-oxide RRAM,” Proc. IEEE, vol. 100, no. 6, pp. 1951–1970, May 2012.
[4] A. Sawa, “Resistive switching in transition metal oxides.” Mater. Today, vol. 11, no. 6, pp.28–36, Jun. 2008.
[5] R. Waser, and M. Aono, “Nanoionics-based resistive switching memories.” Nature Mater., vol. 6, pp. 833–840, Nov. 2007.
[6] F.C. Chiu, “A Review on Conduction Mechanisms in Dielectric Films.” Advances in Materials Science and Engineering, vol. 2014, 18 pages, Feb. 2014.
[7] E.W. Lim, and R. Ismail, “Conduction mechanism of valence change resistive switching memory: a survey.” Electronics, vol. 4, no. 3, pp. 586-613, Sep. 2015.
[8] Y.Q. Zhu, H.Qian, L.F. Wang, L.Wang, and J.Y. Tang “Measurement and analysis of substrate leakage current of RF mems capacitive switches.” Microelectron. Reliab. vol. 54, no. 1, pp. 152–159, Jan. 2014.
[9] B. Majkusiak, P. Palestri, A. Schenk, A.S. Spinelli, C.M. Compagnoni, and M. Luisier, “Modeling and Simulation Approaches for Gate Current Computation.” Nanoscale CMOS, vol. 2, pp. 213–251, Mar. 2013.
[10] P.F. Chiu and B. Nikolic, “A Differential 2R Crosspoint RRAM Array With Zero Standby Current.” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 5, pp. 461-465, May 2015.
[11] J.J. Huang, Y.M Tseng, W.C. Luo, C.W. Hsu, and T.H. Hou, “One selector-one resistor(1S1R) crossbar array for high-density flexible memory applications.” in IEDM Tech. Dig., pp. 733–736, Dec. 2011.
[12] A. Flocke, and T.G. Noll “Fundamental analysis of resistive nanocrossbars for the use in hybrid nano/CMOS-memory.” in Proc. 33rd European Solid-State Circuits Conf. (ESSCIRC), pp. 328–331, Sep. 2007.
[13] J. Liang, and H.S. Wong, “Cross-point memory array without cell selectors—Device characteristics and data storage pattern dependencies.” IEEE Trans. Electron Devices, vol. 57, no. 10, pp. 2531–2538, Oct. 2010.
[14] G.H. Kim, J.H. Lee, Y. Ahn, W. Jeon, S.J. Song, J.Y. Seok, J.H. Yoon, K.J. Yoon, T.J. Park, and C.S. Hwang, “32 × 32 Crossbar Array Resistive Memory Composed of a Stacked Schottky Diode and Unipolar Resistive Memory.” Adv. Funct. Mater., vol. 23, no. 11, pp. 1440–1449, Mar. 2013
[15] M.J. Lee, Y. Park, B.S. Kang, S.E. Ahn, C. Lee, K. Kim, W. Xianyu, G. Stefanovich, J.H. Lee, S.J. Chung, Y.H. Kim, C.S. Lee, J.B Park , I.G. Baek, and I.K. Yoo, “2-stack 1D-1R cross-point structure with oxide diodes as switch elements for high density resistance RAM applications.” in IEDM Tech. Dig., pp. 771–774, Dec. 2007
[16] J.J. Huang, Y.M. Tseng, C.W. Hsu, and T.H. Hou, “Bipolar Nonlinear Ni/TiO2/Ni Selector for 1S1R Crossbar Array Applications.” in IEEE Electron Device Letters, vol. 32, no. 10, pp. 1427-1429, Oct. 2011
[17] J.J. Huang, Y.M. Tseng, W.C. Luo, C.W. Hsu, and T.H. Hou “One selector-one resistor (1S1R) crossbar array for high-density flexible memory applications.” in IEDM Tech. Dig., pp. 733–736, Dec. 2011.
[18] Y.Y. Chen, B. Govoreanu, L. Goux, R. Degraeve, A. Fantini, G.S. Kar, D. J. Wouters, G. Groeseneken, J.A. Kittl, M. Jurczak, and L. Altimime, “Balancing SET/RESET Pulse for >1010 Endurance in HfO2/Hf 1T1R Bipolar RRAM.” in IEEE Transactions on Electron Devices, vol. 59, no. 12, pp. 3243-3249, Dec. 2012
[19] Y.Y. Chen, L. Goux, S. Clima, B. Govoreanu, R. Degraeve, G.S. Kar, A. Fantini, G. Groeseneken, D.J. Wouters, and M. Jurczak, “Endurance/Retention Trade-off on HfO2/Metal Cap 1T1R Bipolar RRAM.” in IEEE Transactions on Electron Devices, vol. 60, no. 3, pp. 1114-1121, Mar. 2013
[20] B. Hudec, C.W. Hsu, I.T. Wang, W.L. Lai, C.C. Chang, T. Wang, K. Fröhlich, C.H. Ho, C.H. Lin, and T.H. Hou “3D resistive RAM cell design for high-density storage class memory—a review.” Sci. China Inf. Sci., vol. 59, no. 61403, pp. 1-21, Mar. 2016.
[21] Y. Deng, H.Y. Chen, B. Gao, S. Yu, S.C. Wu, L. Zhao, B. Chen, Z. Jiang, X. Liu, T.H. Hou, Y. Nishi, J. Kang, and H.S. Wong “Design and optimization methodology for 3D RRAM arrays.” in IEDM Tech. Dig., pp. 629–632, Dec. 2013.
[22] H.Y. Chen, S. Brivio, C.C. Chang, J. Frascaroli, T.H. Hou, B. Hudec, M. Liu, H. Lv, G. Molas, J. Sohn, S. Spiga, V.M. Teja, E. Vianello, H.S. Wong, “Resistive random access memory (RRAM) technology: From material, device, selector 3D integration to bottom-up fabrication.” J. Electroceram., vol. 39, pp. 21–38, 2017.
[23] H. Tanaka, M. Kido, K. Yahashi, M. Oomura, R. Katsumata, M. Kito, Y. Fukuzumi, M. Sato, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi, and A. Nitayama, ‘‘Bit cost scalable technology with punch and plug process for ultra high density flash memory.’’ in Sym. on VLSI Technology, pp. 14–15, Jan. 2007
[24] S.G. Park, M.K. Yang, H. Ju, D.J. Seong, J.M. Lee, E. Kim, S. Jung, L. Zhang, Y.C. Shin, I.G. Baek, J. Choi, H.K. Kang, and C. Chung, “A non-linear ReRAM cell with sub-1μA ultralow operating current for high density vertical resistive memory (VRRAM).” 2012 International Electron Devices Meeting, San Francisco, CA, pp. 20.8.1-20.8.4, Dec. 2012
[25] Y. Demchenko, C. Laat, P. Membrey, “Defining architecture components of the Big Data Ecosystem.” 2014 International Conference on Collaboration Technologies and Systems (CTS). IEEE, Jul. 2014.
[26] P.A. Merolla1, J.V. Arthur, R. Alvarez-Icaza1, A.S. Cassidy, J. Sawada, F. Akopyan, B.L. Jackson, N. Imam, C. Guo, Y. Nakamura, B. Brezzo, I. Vo, S.K. Esser, R. Appuswamy, B. Taba1, A. Amir, M.D. Flickner, W.P. Risk, R. Manohar, and D.S. Modha, “A million spiking-neuron integrated circuit with a scalable communication network and interface.” Science, vol. 345, no. 6197, pp. 668-673, Aug. 2014.
[27] C. Mead, Analog VLSI and Neural Systems, Addison-Wesley, Boston, MA, , p. 3, Jan. 1989.
[28] J. Backus, “Can programming be liberated from the von Neumann style? A functional style and its algebra of programs.” Communications of the ACM vol. 21.8, pp. 613-641, 1978.
[29] D.O. Hebb, The Organization of Behavior, John Wiley & Sons, New York, 1949.
[30] S Lowel and W Singer “Selection of intrinsic horizontal connections in the visual cortex by correlated neuronal activity.” Science, vol. 255, no. 5041, pp. 209-212, Jan. 1992.
[31] C. Mead, “Analog VLSI and neutral systems.” NASA STI/Recon Technical Report A 90, 1989.
[32] G. Cauwenberghs, “Reverse engineering the cognitive brain.” Proc. Nat. Academy Sci.,vol. 110, no. 39, pp. 15512–15513, Sep. 2013.
[33] L. Chua, “Memristor-The missing circuit element.” in IEEE Transactions on Circuit Theory, vol. 18, no. 5, pp. 507-519, Sep. 1971.
[34] M.J. Tour and T. He, “The fourth element.” Nature, vol. 453, pp. 42–43, Apr. 2008.
[35] D.B. Strukov, G.S. Snider, D.R. Stewart, and R.S. Williams “The missing memristor found.” Nature, vol. 453, no.7191, pp. 80-83, May 2008.
[36] S. Yu, B. Gao, Z. Fang, H. Yu, J. Kang, and H.S. Wong, “A neuromorphic visual system using RRAM synaptic devices with sub-pJ energy and tolerance to variability: Experimental characterization and large-scale modeling.” 2012 International Electron Devices Meeting. IEEE, pp. 10.4.1-10.4.4, Dec. 2012.
[37] J.R. Hughes, “Post-tetanic potentiation.” Physiological reviews, vol. 38.1, pp. 91-113, 1958.
[38] K. Gerrow and A. Triller “Synaptic stability and plasticity in a floating world.” Current opinion in neurobiology, vol. 20, no.5, pp. 631-639, Oct. 2010.
[39] A. Artola and W. Singer. “Long-term depression of excitatory synaptic transmission and its relationship to long-term potentiation.” Trends in neurosciences,vol. 16, no. 11, pp. 480-487, 1993.
[40] S.H. Jo, T. Chang, I. Ebong, B.B. Bhadviya, P. Mazumder, and W. Lu “Nanoscale memristor device as synapse in neuromorphic systems.” Nano letters, vol. 10, no. 4, pp. 1297-1301, Mar. 2010.
[41] D. Kuzum, S. Yu, and H.S. Wong, “Synaptic electronics: Materilas, devices and applications.” Nanotechnology, vol. 24, no. 382001, Jun. 2013.
[42] C.Z. Ramos, L.A.C. Mesa, J.A.P. Carrasco, T. Masquelier, T.S. Gotarredona, and B.L. Barranco, “On spike-timing-dependent-plasticity, memristive devices, and building a self-learning visual cortex.” Frontiers in neuroscience, vol. 5, no. 26, Mar. 2011.
[43] G.Q. Bi and M.M. Poo, “Synaptic modifications in cultured hippocampal neurons: dependence on spike timing, synaptic strength, and postsynaptic cell type.” Journal of neuroscience, vol. 18, no. 24, pp. 10464-10472, Dec. 1998
[44] S. Yu, Y. Wu, R. Jeyasingh, D. Kuzum, and H.S.P. Wong, “An electronic synapse device based on metal oxide resistive switching memory for neuromorphic computation.” IEEE Transactions on Electron Devices, vol. 58, no. 8, pp. 2729-2737, Aug. 2011.
[45] B.L. Barranco and T.S. Gotarredona, “Memristance can explain spike-time-dependent-plasticity in neural synapses.” Nature precedings, vol. 3010, no. 1, Mar. 2009.
[46] J. Liang and H.S.P. Wong, “Cross-point memory array without cell selectors—Device characteristics and data storage pattern dependencies.” IEEE Transactions on Electron Devices, vol. 57, no.10, pp. 2531-2538, Oct. 2010.
[47] X. Yang, B.J. Choi, A.B.K. Chen, and I.W. Chen, “Cause and prevention of moisture-induced degradation of resistance random access memory nanodevices.” ACS nano, vol. 7, no. 3, pp. 2302-2311, Feb. 2013.
[48] C.T. Wang and C.L. W, “Electrical sensing properties of silica aerogel thin films to humidity.” Thin Solid Films, vol. 496, no.2, pp. 658-664, Feb. 2006.
[49] W. Kim, A. Javey, O. Vermesh, Q. Wang, Y. Li, and H. Dai, “Hysteresis caused by water molecules in carbon nanotube field-effect transistors.” Nano Letters, vol. 3, no.2, pp. 193-198, Jan. 2003.
[50] I. Valov and T. Tsuruoka, “Effects of moisture and redox reactions in VCM and ECM resistive switching memories.” Journal of Physics D: Applied Physics, vol. 51, no .41, pp. 413001-413018, Aug. 2018.
[51] A. Chen, “Area and thickness scaling of forming voltage of resistive switching memories.” IEEE electron device letters, vol. 35, no.1, pp. 57-59, Nov. 2013.
[52] T. Diokh, E.L. Roux, S. Jeannot, M.G. Jean, P. Candelier, J.F. Nodin, V.Jousseaume, L. Perniola, H. Grampeix, T. Cabout, E. Jalaguier, M. Guillermet, B.D. Salvo, “Investigation of the impact of the oxide thickness and RESET conditions on disturb in HfO2-RRAM integrated in a 65nm CMOS technology.” 2013 IEEE International Reliability Physics Symposium (IRPS). IEEE, Jun. 2013.
[53] P.Y. Chen, B. Lin, I.T. Wang, T.H. Hou, J. Ye, S. Vrudhula, J.S. Seo, Y. Cao, and S. Yu, “Mitigating effects of non-ideal synaptic device characteristics for on-chip learning.” 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, Nov. 2015.
[54] B. Ku, Y. Abbas, S. Kim, A.S. Sokolov, Y.R. Jeon, and C. Choi, “Improved resistive switching and synaptic characteristics using Ar plasma irradiation on the Ti/HfO2 interface.” Journal of Alloys and Compounds, vol. 797, no. 15, pp. 277-283, Aug. 2019.
[55] “https://en.wikipedia.org/wiki/Atomic_force_microscopy”
[56] “http://mcff.mtu.edu/acmal/electronmicroscopy/MA_EDS_Basic_Science.htm”
[57] “https://www.embl.de/services/core_facilities/em/services/fibsem/”
[58] “https://en.wikipedia.org/wiki/Transmission_electron_microscopy”
[59] M.S. Zafar, I. Farooq, M. Awais, S. Najeeb, Z. Khurshid, S. Zohaib, “Bioactive surface coatings for enhancing osseointegration of dental implants.” Biomedical, therapeutic and clinical applications of bioactive glasses. Woodhead Publishing, pp. 313-329, 2019
[60] C. Wang and T. Suga, “Investigation of fluorine containing plasma activation for room-temperature bonding of Si-based materials.” Microelectronics Reliability, vol. 52, no. 2, pp. 347-351, Feb. 2012.
[61] I.K. Oh, J. Tanskanen, H. Jung, K. Kim, M.J. Lee, Z. Lee, S.K. Lee, J.H. Ahn, C.W. Lee, K. Kim, H. Kim, and H.B.R. Lee, “Nucleation and growth of the HfO2 dielectric layer for graphene-based devices.” Chemistry of Materials, vol. 27, no.17, pp. 5868-5877, Aug. 2015.
[62] P. Calka, M. Sowinska, T. Bertaud, D. Walczyk, J. Dabrowski, P. Zaumseil, C. Walczyk, A. Gloskovskii, X. Cartoixa,̀ J. Suñ e,́ and T. Schroeder, “Engineering of the Chemical Reactivity of the Ti/HfO2 Interface for RRAM: Experiment and Theory.” ACS applied materials & interfaces, vol. 6, no. 7, pp. 5056-5060, Mar. 2014.
[63] J.A. Dean, Lange's handbook of chemistry. New York: McGraw-Hill, vol. 15, 1992.
[64] D. Ielmini, “Modeling the universal set/reset characteristics of bipolar RRAM by field-and temperature-driven filament growth.” IEEE Transactions on Electron Devices, vol. 58, no.12, pp. 4309-4317, Dec. 2011.
[65] J. Hölzl, and F.K. Schulte, “Work function of metals.” Solid surface physics. Springer, Berlin, Heidelberg, pp. 1-150, 1979.
[66] A. Prakash, D. Deleruyelle, J. Song, M. Bocquet, and H. Hwang, “Resistance controllability and variability improvement in a TaOx-based resistive memory for multilevel storage application.” Applied Physics Letters, vol. 106, no. 23, pp. 233104.1-233104.4, Jan. 2015.
[67] A. Prakash, J. Park, J. Song, J. Woo, E.J. Cha, and H. Hwang, “Demonstration of low power 3-bit multilevel cell characteristics in a TaOx-based RRAM by stack engineering.” IEEE Electron Device Letters, vol. 36, no. 1, pp. 32-34, Jan. 2014.
[68] T. Hasegawa, T. Ohno, K. Terabe, T. Tsuruoka, T. Nakayama, J. K. Gimzewski, and M. Aono, “Learning abilities achieved by a single solid‐state atomic switch.” Advanced materials, vol. 22, no. 16, pp. 1831-1834, Apr. 2010.
[69] I.T. Wang, C.C. Chang, L.W. Chiu, T. Chou, and T.H. Hou, “3D Ta/TaOx/TiO2/Ti synaptic array and linearity tuning of weight update for hardware neural network applications.” Nanotechnology, vol. 27, no. 36 365204.1-365204.8, Aug. 2016.
[70] D.H. Kwon, K.M. Kim, J.H. Jang, J.M. Jeon, M.H. Lee, G.H. Kim, X.S. Li, G.S. Park, B. Lee, S. Han, M. Kim, and C.S. Hwang, “Atomic structure of conducting nanofilaments in TiO2 resistive switching memory.” Nature nanotechnology, vol. 5, no. 2, pp. 148-153, Jan. 2010.
[71] B.J. Choi, D.S. Jeong, S.K. Kim, C. Rohde, S. Choi, J.H. Oh, H.J. Kim, C.S. Hwang, K. Szot, R. Waser, B. Reichenberg, and S. Tiedke, “Resistive switching mechanism of TiO2 thin films grown by atomic-layer deposition.” Journal of applied physics, vol. 98, no. 3, pp. 033715.1-033715.10, Aug. 2005.
[72] S. Cho, J. Jung, S. Kim, and J.J. Pak, “Conduction mechanism and synaptic behaviour of interfacial switching AlOσ-based RRAM.” Semiconductor Science and Technology, vol. 35, no. 8, pp. 085006.1- 085006.7, Jun. 2020.
[73] S. Chandrasekaran, F.M. Simanjuntak, D. Panda, and T.Y. Tseng, “Enhanced synaptic linearity in ZnO-based invisible memristive synapse by introducing double pulsing scheme.” IEEE Transactions on Electron Devices, vol. 66, no. 11, pp. 4722-4726, Nov. 2019.
[74] S. Chandrasekaran, F.M. Simanjuntak, R. Saminathan, D. Panda, and T.Y. Tseng, “Improving linearity by introducing Al in HfO2 as a memristor synapse device.” Nanotechnology, vol. 30, no. 44, pp. 445205.1-445205.9, Aug. 2019.
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