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系統識別號 U0026-1908201322593600
論文名稱(中文) 應用於射頻收發機系統之寬頻再生式除頻器、可調式衰減器與超低功耗倍頻器之研製
論文名稱(英文) Broadband Frequency Dividers, Variable Attenuator, and Ultra-Low-Power Frequency Multiplier for RF Transceiver System Applications
校院名稱 成功大學
系所名稱(中) 微電子工程研究所碩博士班
系所名稱(英) Institute of Microelectronics
學年度 101
學期 2
出版年 102
研究生(中文) 吳承翰
研究生(英文) Cheng-Han Wu
學號 Q16001084
學位類別 碩士
語文別 中文
論文頁數 120頁
口試委員 指導教授-王永和
口試委員-洪茂峰
口試委員-王瑞祿
口試委員-蔡俊輝
口試委員-陳家豪
中文關鍵字 收發機  再生式除頻器  CML  鎖相迴路  可調式衰減器  倍頻器 
英文關鍵字 transceiver  regenerative divider  current-mode-logic  phase-locked loop  variable attenuator  multiplier 
學科別分類
中文摘要 本論文主要研究應用於Ku至Ka頻段 (12-40GHz) 之射頻收發機電路元件,首先使用TSMC 90nm CMOS製程研製一個具有除四及正交相位輸出的再生式除頻器,本次設計是使用了次諧波混頻器、中央抽頭變壓器及源極注入CML除二電路,形成一再生式除頻器架構。由變壓器設計的源極注入CML電路,可改善傳統差動注入CML的高頻雜散電容效應,提高注入功率與操作頻寬,提升再生式除頻器的鎖頻範圍,不須再使用級間buffer,節省除頻器功耗與面積。量測後的鎖頻範圍為20.1-24.8GHz,核心電路的消耗功率為13.7mW,晶片面積為0.69 × 0.85 mm2。
第二部分為使用正交注入式CML的除三再生式除頻器與除五再生式除頻器的研製。其架構為使用兩組Gilbert Mixer與帶通濾波器並結合正交注入式的CML電路,來實現兩顆具有高除數、寬鎖頻範圍以及正交輸入正交輸出功能的再生式除頻器。與傳統差動注入式CML比較,運用正交注入式CML電路,能有效改善再生式除頻器的鎖頻範圍,並應用於正交鎖相迴路。關於除三與除五的除頻器量測結果顯示,核心電路消耗功率分別為10.73mW/ 14.8mW,且擁有12.5-23GHz (59%) / 7.2-19GHz (90%)的超寬鎖頻範圍及高達52.3/ 133.5的FOM值。
第三部分為一個新的相位抵消式可調式衰減器,架構上使用了Lange Coupler、反射型相移器(RTPS)以及Wilkinson Power Combiner,使用相位合成抵消的方式來作功率的衰減,研製一可調式衰減器。本次設計架構並非直接使用主被動元件來衰減功率,能夠降低元件的高頻寄生效應,改善操作頻率以及頻寬,並能有低的功率損失和寬廣的衰減範圍。此電路量測的操作頻寬為30-40GHz,可調的衰減量為4.5-23.7dB之間,範圍約為19.2dB,在操作頻寬下的反射損失皆大於10dB。
第四部分為提出新式諧波增強技術的超低功耗五倍頻器。架構為使用一組交叉耦合電晶體對與次諧波混頻器作疊接而成,此次創新概念使用交叉耦合對來提供迴路增益可有效增強高次諧波功率,解決高倍數倍頻器因高次諧波訊號功率過小而難以實現的問題,此外架構上同時使用電流共用技術以降低核心電路功耗。經由模擬,本次設計的倍頻器具有五倍的高倍數、23-27.5GHz的操作頻寬、大於20dB的諧波抑制能力、以及低達0.18mW的超低功耗。
英文摘要 The main research of this thesis is for the application of RF receiver circuit in Ku-Ka band. First, a divide-by-4 regenerative frequency divider (RFD) with quadrature outputs is implemented in TSMC 90 nm CMOS process. The structure which uses feedback to combine sub-harmonic mixer, center-tap transformer, and source-injection current-mode-logic (CML) circuit becomes a regenerative divider. The source-injection CML circuit can improve the parasitic effects of the conventional differential CML circuit which operate in high frequency to increase the injection power of the CML and to operate in high frequency. Therefore, the design has wide locking range and need no inter-stage buffer, so it can save power consumption and chip area. The core circuit consumes 13.7mW, the locking range is 20.1-24.8 GHz, and the chip size is 0.69 x 0.85 mm2.
The second part of this thesis presents a divide-by-3 and a divide-by-5 regenerative frequency divider which use quadrature-injection CML to implement by TSMC 90 nm CMOS process. The architecture consists of two Gilbert mixers, two bandpass filters, and quadrature-injection CML to realize two frequency divider with high division number, wide locking range, and the function of quadrature inputs and outputs. Compared with traditional differential-injection CML, the locking range of quadrature-injection CML is improved extensively. Furthermore, the proposed divider can use in quadrature phase-locked loop. The power consumption of the measured divide-by-3 divider and the measured divide-by-5 divider is 10.73mW and 14.8mW, the locking range is 12.5-23GHz (59%) and 7.2-19GHz (90%), and the FOM is up to 52.3 and 133.5.
The third part used 0.25-μm GaN pHEMT process to demonstrate a fixed-phase variable attenuator with novel phase-cancellation technique. The circuit with phase-cancellation technique constitutes by Lange coupler, reflective type phase shifter, and Wilkinson power combiner to control power level and achieve a variable attenuator. The new structure avoided signal power passing through the dissipative devices, so it can reduce the parasitic effects of the devices. Therefore, it has low power loss, wide operation range, and good attenuation range. The measured bandwidth is 30-40 GHz, the attenuation range is about 19.2dB from 4.5-23.7dB, and the return loss at operation bandwidth is larger than 10 dB.
The fourth part proposed an ultra-low-power quintupler with novel harmonic-enhanced technique by TSMC 90 nm CMOS process. The circuit combines a sub-harmonic mixer and a cross-coupled pair transistor to generate a five times frequency signal. The new idea is that by using the cross-coupled pair transistor to provide circuit loop gain can enhance the high-order harmonic power and solves the high-order harmonic power is too small to realize high multiply number. In addition, the circuit also uses current-reuse technique to reduce power consumption. By simulation, this quintupler has as five times as high multiply number, the operation range is 23-27.5GHz , the harmonic suppression is larger than 20 dB, and the power is low down to 0.18mW.
論文目次 目錄
中文摘要 I
Abstract III
致謝 VI
目錄 VIII
圖目錄 XIII
表目錄 XIX

第一章 1
緒論 1
1.1研究發展與背景 1
1.2章節概述 2
1.3參考文獻 3
第二章 4
收發機架構與基礎理論 4
2.1收發機的架構簡介 4
2.2鎖相迴路架構簡介 5
2.3基礎理論 7
2.3.1 雜訊指數 7
2.3.2 動態範圍 7
2.3.3 輸入三階截斷點 8
2.4除頻器的規格參數 10
2.4.1輸入靈敏度(Input Sensitivity) 10
2.4.2輸出功率(Output Power) 11
2.4.3相位雜訊(Phase Noise) 11
2.4.4鎖頻範圍(Locking Range) 11
2.5可調式衰減器的規格參數 11
2.5.1衰減範圍(Attenuation Range) 12
2.5.2相位變化量(Phase Variation) 12
2.5.3反射損失(Return Loss) 12
2.5.4介入損失(Insertion Loss) 12
2.6倍頻器的規格參數 13
2.6.1輸出功率(Output Power) 13
2.6.2相位雜訊(Phase Noise) 13
2.6.3頻率操作範圍(Operation Range) 13
2.6.4諧波抑制能力(Harmonic Suppression) 14
2.7參考文獻 14
第三章 16
除頻器 16
3.1除頻器相關研究發展 16
3.1.1 鎖相迴路之理論基礎 16
3.1.2 除頻器架構簡介 17
3.2使用變壓器耦合技術之除四正交再生式除頻器 18
3.2.1 研究動機 18
3.2.2除頻器電路架構與設計 19
3.2.3電路佈局與測試 28
3.2.4電路模擬與量測結果 31
3.2.5結果與討論 37
3.3具有正交輸入與正交輸出之寬頻除五再生式除頻器及除三再生式除頻器 38
3.3.1 研究動機 38
3.3.2正交輸入與正交輸出之再生式除頻器電路架構與設計 40
3.3.2.1除五再生式除頻器電路架構與設計 40
3.3.2.2除三再生式除頻器電路架構與設計 46
3.3.3電路佈局與測試 52
3.3.3.1除五再生式除頻器電路佈局與測試 52
3.3.3.2除三再生式除頻器電路佈局與測試 54
3.3.4電路模擬與量測結果 57
3.3.4.1除五再生式除頻器電路模擬與量測結果 57
3.3.4.2除三再生式除頻器電路模擬與量測結果 60
3.3.5結果與討論 66
3.4參考文獻 67
第四章 72
衰減器 72
4.1衰減器相關研究發展 72
4.1.1可調式衰減器之應用 72
4.1.2 可調式衰減器架構簡介 73
4.2使用相位抵消技術之輸出恆相可調式衰減器 74
4.2.1 研究動機 74
4.2.2可調式衰減器電路架構與設計 75
4.2.3電路佈局與測試 82
4.2.4電路模擬與量測結果 84
4.2.5結果與討論 89
4.3參考文獻 90
第五章 93
倍頻器 93
5.1倍頻器相關研究發展 93
5.1.1鎖相迴路之理論基礎 93
5.1.2 倍頻器架構簡介 95
5.2使用新型諧波增強技術之超低功耗五倍頻器 96
5.2.1 研究動機 96
5.2.2倍頻器電路架構與設計 97
5.2.3電路佈局與測試 101
5.2.4電路模擬結果 103
5.2.5結果與討論 110
5.3參考文獻 112
第六章 115
結論 115
第七章 119
未來研究 119

圖目錄
圖2.1收發機基本架構 4
圖2.2鎖相迴路基本架構 6
圖2.3 1dB增益壓縮點與動態範圍 8
圖2.4非線性系統的三階交互調變 9
圖2.5三階截斷點 10
圖3.1鎖相迴路之基本架構 16
圖3.2傳統再生式除頻器之架構方塊圖 18
圖3.3變壓器耦合技術之除四再生式除頻器架構方塊圖 20
圖3.4變壓器耦合技術之除四再生式除頻器電路架構圖 21
圖3.5次諧波混頻器以及帶通濾波器之電路架構 22
圖3.6八邊形中央抽頭式變壓器 23
圖3.7變壓器電感值與Q值 24
圖3.8除二源極注入靜態除頻器之電路架構 25
圖3.9為源極注入CML 除頻器(上)以及一般傳統差動注入CML 除頻器電路(下)架構圖 26
圖3.10 CML注入電流的模擬結果 27
圖3.11輸出緩衝級電路 28
圖3.12電路佈局圖 29
圖3.13晶片顯微照 30
圖3.14量測示意圖 31
圖3.15輸出頻譜量測結果(Fin= 24.8GHz, Pin= -5dBm) 32
圖3.16輸出頻譜量測結果(Fin=20.1 GHz, Pin=0 dBm) 33
圖3.17輸出波形量測結果(I-green、Q-red) 33
圖3.18輸入靈敏度量測結果 34
圖3.19正交輸出功率量測結果 34
圖3.20電路自振之輸出頻譜量測結果 35
圖3.21相位雜訊量測結果 35
圖3.22傳統正交鎖相迴路之架構方塊圖 38
圖3.23使用正交除頻器之鎖相迴路架構方塊圖 39
圖3.24除五再生式除頻器之架構方塊圖 41
圖3.25具有正交輸入以及正交輸出之寬頻除五再生式除頻器電路架構圖 42
圖3.26混頻器以及帶通濾波器之電路架構 43
圖3.27除二正交注入CML除頻器之電路架構 44
圖3.28為正交注入CML除頻器(上)以及傳統差動注入CML除頻器(下)架構圖 45
圖3.29為輸出緩衝級之電路架構 46
圖3.30除三再生式除頻器之架構方塊圖 47
圖3.31具有正交輸入以及正交輸出之寬頻除三再生式除頻器電路架構圖 48
圖3.32混頻器以及帶通濾波器之電路架構 49
圖3.33除二正交注入CML除頻器之電路架構 50
圖3.34為正交注入CML除頻器(上)以及傳統差動注入CML除頻器(下)架構圖 51
圖3.35為輸出緩衝級之電路架構 52
圖3.36電路佈局圖 53
圖3.37晶片顯微照 54
圖3.38電路佈局圖 55
圖3.39晶片顯微照 56
圖3.40為量測示意圖 57
圖3.41輸出頻譜量測結果(Fin= 13GHz, Pin= 0dBm) 58
圖3.42電路自振之輸出頻譜量測結果 59
圖3.43相位雜訊量測結果 59
圖3.44輸入靈敏度量測結果 60
圖3.45正交輸出功率量測結果 60
圖3.46輸出頻譜量測結果(Fin= 17.5GHz, Pin= 0dBm) 61
圖3.47電路自振之輸出頻譜量測結果 62
圖3.48相位雜訊量測結果 62
圖3.49輸入靈敏度量測結果 63
圖3.50正交輸出功率量測結果 63
圖4.1可調式衰減器用於收發機系統示意圖 73
圖4.2傳統可調式衰減器架構方塊圖 73
圖4.3相位抵消技術之可調式衰減器架構方塊圖 76
圖4.4為相位抵消式衰減示意圖 77
圖4.5 Lange Coupler之電路架構 78
圖4.6反射型相移器之電路架構 79
二極體偏壓在0 V時之S參數與相位移角度 80
二極體偏壓在2 V時之S參數與相位移角度 81
圖4.7二極體偏壓在0V與2V時之S參數與相位移角度 81
圖4.8 Wilkinson Power Combiner電路架構 81
圖4.9電路佈局圖 82
圖4.10晶片顯微照 83
圖4.11量測示意圖 84
圖4.12可調式衰減器之S21、S11參數模擬結果 85
圖4.13可調式衰減器的S21 86
圖4.14可調式衰減器的S11 87
圖4.15不同偏壓下的衰減量 87
圖4.16不同衰減量的相位變化 87
圖4.17衰減器線性度量測結果 88
圖5.1傳統鎖相迴路之架構方塊圖 94
圖5.2使用倍頻器之鎖相迴路架構方塊圖 95
圖5.3傳統倍頻器之架構方塊圖 96
圖5.4使用諧波增強技術之倍頻器架構方塊圖 97
圖5.5利用新式諧波增強技術之五倍頻器架構方塊圖 97
圖5.6次諧波混頻器與交叉耦合對架構圖 99
圖5.7無使用交叉耦合對的四倍頻與二倍頻模擬結果 100
圖5.8使用交叉耦合對的四倍頻與二倍頻模擬結果 100
圖5.9輸出緩衝器 101
圖5.10電路佈局圖 102
圖5.11為量測示意圖 103
(a) Pre-layout simulation 105
(b) Post-layout simulation 105
圖5.12五倍頻器之輸出頻譜模擬結果 105
(a) Pre-layout simulation 106
(b) Post-layout simulation 106
圖5.13輸入訊號(fin=4.9GHz)以及輸出訊號(fout=24.5GHz)之時態模擬結果 106
(a) Pre-layout simulation 107
(b) Post-layout simulation 107
圖5.14五倍頻器之輸出相位以及相位差之模擬結果 107
(a) Pre-layout simulation (b) Post-layout simulation 108
圖5.15相位雜訊之模擬結果 108
(a) Pre-layout simulation 108
(b) Post-layout simulation 109
圖5.16基頻、二倍、三倍、四倍與五倍頻輸出功率對於輸出頻率之模擬結果 109
圖7.1使用交叉耦合對之再生式除頻器架構方塊圖 119
圖7.2使用多組交叉耦合對之高倍數倍頻器架構方塊圖 120

表目錄
表3.1使用變壓器耦合技術之除四再生式除頻器預計規格以及量測結果列表 36
表3.2使用變壓器耦合技術之除四再生式除頻器文獻比較表 36
表3.3具有正交輸入與正交輸出之寬頻除五再生式除頻器預計規格以及量測結果列表 64
表3.4具有正交輸入與正交輸出之寬頻除三再生式除頻器預計規格以及量測結果列表 64
表3.5具有正交輸入與正交輸出之寬頻除五及除三再生式除頻器文獻比較表 65
表4.1使用相位抵消技術之輸出恆相可調式衰減器預計規格以及模擬結果列表 88
表4.2使用相位抵消技術之輸出恆相可調式衰減器文獻比較表 88
表5.1使用新型諧波增強技術之超低功耗五倍頻器預計規格以及模擬結果列表 109
表5.2使用新型諧波增強技術之超低功耗五倍頻器文獻比較表 110
參考文獻 Chapter 1
[1] B. Razavi,“RF IC design challenges,”Design Automation Conference, 1998.Proceedings, 15-19 June 1988.

Chapter 2
[1] B. Razavi, RF Microelectronics, Upper Saddle River, NJ: Prentice Hall, 1998.
[2] D. M. Pozar, Microwave and RF design of wireless systems, New York :JohnWiley, 2001.
[3] S. A. Mass, Microwave Mixers, 2nd ed. Boston, MA: Artech House.
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[5] S. A. Maas, Nonlinear Microwave and RF circuits 2nd ed., Artech House, 2003.
[6] S. A. Maas, The RF and Microwave Circuit Design Cookbook, Artech House,1998.

Chapter 3
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[5] H. Zheng and H. C. Luong, “Ultra-low-voltage 20-GHz frequency dividers using transformer feedback in 0.18-μm CMOS process, ” IEEE J. Solid-State Circuits, vol. 43, no. 10, pp. 2293-2302, Oct. 2008.
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[7] Y. T. Chen, M. W. Li, H. C. Kuo, T. H. Huang, and H. R. Chuang, “Low-voltage K-band divide-by-3 injection-locked frequency divider with floating-source differential injector, ” IEEE Trans. Microw. Theory Tech., vol. 60, no. 1, pp. 60-67, Jan. 2012.
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Chapter 4
[1] Y. Y. Huang, W. Woo, C. H. Lee, and J. Laskar, “A CMOS wide-bandwidth high-power linear-in-dB variable attenuator using body voltage distribution method,” IEEE Radio Frequency Integrated Circuits Symposium, pp. 303-306, 2010.
[2] C. E. Saavedra, and B. R. Jackson, “Voltage-variable attenuator MMIC using phase cancellation,” IEE Proceedings-Circuits, Devices and Systems, vol. 153, no.5 , pp.442-446, Oct. 2006.
[3] C. W. Wang, H. S. Wu, M. J. Chiang, and C. K. C. Tzuang, “A 24 GHz CMOS miniaturized phase-invertible variable attenuator incorporating edge-coupled synthetic transmission lines,” IEEE Microwave Symposium Digest, 2009. MTT'09. IEEE MTT-S International. 2009. pp. 841-844.
[4] K. Sun, M. Choi, and D. Weide, “A PIN diode controlled variable attenuator using a 0-dB branch-line coupler,” IEEE Microwave and Wireless Component Letters, vol. 15, no. 6, pp. 440-442, Jun. 2005.
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[13] C. R. Trent and T. M. Weller, “S-band reflection type variable attenuator,” IEEE Microw. Wireless Compon. Lett., vol. 12, no. 7, pp.243 -245, Jul. 2002.

Chapter 5
[1] P. K. Tsai, and T. H. Huang, “Integration of current-reused VCO and frequency tripler for 24-GHz low-power phase-locked loop applications,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, no. 4, pp. 199–203, Apr. 2012.
[2] C. N. Kuo, H. S. Chen, and T. C. Yan, “A K-band CMOS quadrature frequency tripler using sub-harmonic mixer,” IEEE Microw. Wirel. Compon. Lett., vol. 19, no. 12, pp.822-824, Dec. 2009.
[3] E. Monaco, M. Pozzoni, F. Svelto, and A. Mazzanti, “Injection-locked CMOS frequency doublers for u-Wave and mm-Wave applications,” IEEE Journal of Solid-State Circuits, vol. 45, no.8, pp.1565, Aug. 2010.
[4] K. Y. Lin, J. Y. Huang, and S. C. Shin, “A K-band CMOS distributed doubler with current-reuse technique,” IEEE Microw. Wirel. Compon. Lett., vol. 19, no. 5, pp. 308-310, Mar. 2009.
[5] J. H. Chen, and H. Wang, “A high gain, high power K-band frequency doubler in 0.18 um CMOS process,” IEEE Microw. Wirel. Compon. Lett., vol. 20, no. 9, pp.522-524, Sep. 2010.
[6] M. C. Chen, and C. Y. Wu, “Design and analysis of CMOS subharmonic injection-locked frequency triplers,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 8, pp. 1869-1878, Aug. 2008.
[7] Y. T. Lo, and J. F. Kiang, “A 0.18 um CMOS self-mixing frequency tripler,” IEEE Microw. Wirel. Compon. Lett., vol. 22, no. 2, pp. 79-81, Feb. 2012.
[8] B. R. Jackson, F. Mazzilli, and C. E. Saavedra, “A frequency tripler using a subharmonic mixer and fundamental cancellation,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 5, pp.1083-1090, May. 2009.
[9] N. C. Kuo, J. C. Kao, Z. M. Tsai, K. Y. Lin, and H. Wang, “A 60-GHz frequency tripler with gain and dynamic-range enhancement,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 3, pp.660-671, Mar. 2011.
[10] P. K. Tsai, C. Y. Liu, and T. H. Huang, “A CMOS voltage controlled oscillator and frequency tripler for 22-27GHz local oscillator generation,” IEEE Microw. Wirel. Compon. Lett., vol. 21, no. 9, pp.492-494, Sep. 2011.
[11] W. L. Chan, J. R. Long, and J. J. Pekarik, “A 56-to-65GHz injection-locked frequency tripler with quadrature outputs in 90nm CMOS,” ISSCC Dig. Tech. Papers, pp. 480-629, Feb. 2008.
[12] C. N. Kuo, and T. C. Yan, “A 60 GHz injection-locked frequency tripler with spur suppression,” IEEE Microw. Wirel. Compon. Lett., vol. 20, no. 10, pp.560-562, Oct. 2010.
[13] Y. Zheng, and C. E. Saavedra, “A broadband CMOS frequency tripler using a third-harmonic enhanced technique,” IEEE Journal of Solid-State Circuits, vol. 42, no.40, pp.2197-2203, Oct. 2007.
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