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系統識別號 U0026-1908201309401900
論文名稱(中文) 應用於射頻前端系統的多相位除頻器、正交倍頻器及W頻段注入鎖定除頻器
論文名稱(英文) Multi-Phase Frequency Dividers, Quadrature Frequency Multipliers, and A W-band Injection-Locked Frequency Divider for RF Front-End System Applications
校院名稱 成功大學
系所名稱(中) 微電子工程研究所碩博士班
系所名稱(英) Institute of Microelectronics
學年度 101
學期 2
出版年 102
研究生(中文) 黃韋翔
研究生(英文) Wei-Hsiang Huang
學號 Q16001173
學位類別 碩士
語文別 中文
論文頁數 97頁
口試委員 指導教授-王永和
指導教授-蔡宗祐
口試委員-洪茂峰
口試委員-王瑞祿
口試委員-陳家豪
中文關鍵字 除頻器  除四  除八  多相位  倍頻器  五倍  九倍  正交  高功率  耦合線  W頻段 
英文關鍵字 frequency divider  divide-by-4  divide-by-8  multi-phase  frequency multiplier  quintupler  multiplier-by-five  multiplier-by-nice  quadrature  high power  coupled-line  W-band 
學科別分類
中文摘要 本論文主要分成三個部分,首先第一部份探討多相位除頻器之應用,使用TSMC 0.18-μm及90-nm CMOS製程,實現寬頻除四多相位之除頻器及K頻段之除八多相位除頻器。我們創新的利用current mode logic(CML)除頻器正交輸出特性並透過串接結構設計出具有多相位輸出之除四電路,再進一步利用多相位輸出特性搭配四次諧波混頻器設計出新穎的多相位輸出之再生式除八電路。經過量測後得到除四電路的鎖頻範圍操作於1-8.6 GHz,鎖頻範圍百分比高達133%,figure of merit(FOM)值為32.07,晶片面積為0.78 × 0.79 mm^2。除八電路的鎖頻範圍則為16.4-24.4 GHz,鎖頻範圍百分比為39.21%,FOM值則高達94.75,晶片面積為0.808 × 0.9 mm^2。
第二部份則探討正交倍頻器的應用,使用TSMC 90-nm CMOS製程,實現應用於K頻段之正交五倍頻器及77-GHz之正交九倍頻器。在五倍頻器的架構中使用了新穎的再生式電路,此再生式電路具有能夠同時除頻及倍頻的功能,並透過混頻器和三倍頻器的使用,此電路將能夠得到奇次數倍頻的作用。九倍頻器則使用了高轉換效率的正交三倍頻器,並透過耦合線來取代輸出緩衝器以節省功率消耗並同時提升輸出功率。九倍頻器的模擬結果顯示轉換增益在輸出頻率於77 GHz時為-20.69 dB,消耗功率只需4.75 mW,晶片面積為0.6 × 0.69 mm^2。
第三部份使用TSMC 90-nm CMOS製程,實現W頻段高功率耦合線之注入鎖定除頻器,本電路創新之處主要是利用耦合線達成注入訊號及輸出訊號的功能,取代傳統架構中所使用的輸出緩衝器同時節省超過百分之六十的功率消耗,並取得在W頻段下的高功率輸出。經過模擬後電路鎖頻範圍操作於79.3-82.5 GHz,直流消耗功率僅需要1.18 mW,輸出功率皆高於-6 dBm,晶片面積為0.667 × 0.407 mm^2。
英文摘要 Multi-phase frequency dividers, quadrature frequency multipliers, and a W-band injection-locked frequency divider for RF front-end system applications are presented. First, a novel wideband divide-by-4 multi-phase frequency divider using the quadrature output characteristic of the current mode logic and cascade technique was fabricated by the TSMC 0.18 µm CMOS process. A K-band divide-by-8 multi-phase frequency divider implemented by the TSMC 90 nm CMOS process was also achieved by combining the multi-phase frequency divider with a 4X-subharmonic mixer. The measured results of the divide-by-4 and the divide-by-8 dividers indicate that the locking range was 1 GHz to 8.6 GHz (133%) and 16.4 GHz to 24.4 GHz (39.21%), and the figure of merit was up to 32.07 and 94.75, respectively.
Second, a K-band quadrature frequency quintupler and a 77 GHz quadrature frequency multiplier-by-nine were demonstrated using the TSMC 90 nm CMOS process. An innovative regenerating circuit that can simultaneously divide and multiply the frequency was integrated with a mixer to obtain a five-time harmonic in the quintupler. In addition, the use of innovative regenerating circuit with mixer and tripler, odd frequency multipliers can be easily obtained. The implemented multiplier-by-nine was composed of a high conversion gain quadrature frequency tripler with coupled-line as the buffer stage to reduce power consumption and increase power output.
Third, a W-band high-power coupled-line injection-locked frequency divider by using the TSMC 90 nm CMOS process was also presented. The coupled-line technique was mainly used to inject the input signal and drive the next stage effectively. Compared with conventional dividers, the coupled-line technique can save over 60% of power consumption. The locking range is from 79.3 GHz to 82.5 GHz. The DC power consumption is only 1.18 mW, and the output power is higher than -6 dBm. The chip dimension is 0.667 mm × 0.407 mm.
論文目次 中文摘要I
AbstractIII
誌謝V
目錄VI
表目錄VIII
圖目錄IX
第一章緒論1
1.1研究背景1
1.2論文綱要3
第二章基本概念4
2.1 收發機的架構簡介4
2.2 鎖相迴路的架構簡介5
2.3 電路基本參數7
2.3.1輸入靈敏度(Input Sensitivity)7
2.3.2相位雜訊(Phase Noise)7
2.3.3轉換增益(Conversion Gain, CG)8
2.3.4諧波抑制(Harmonic Suppression)9
第三章多相位除頻器之應用10
3.1 多相位除頻器設計目的與動機10
3.1.1直接降頻接收機相關研究發展現況10
3.1.2多相位除頻器研究動機11
3.2寬頻操作之除四多相位除頻器13
3.2.1除四多相位除頻器電路架構13
3.2.2除四多相位除頻器電路設計14
3.2.3電路模擬與測試17
3.2.4結果與討論25
3.3 K頻段之除八多相位除頻器 28
3.3.1 K頻段之除八多相位除頻器電路架構28
3.3.2 K頻段之除八多相位除頻器電路設計29
3.3.3電路模擬與測試34
3.3.4結果與討論42
第四章正交倍頻器之應用44
4.1 正交倍頻器設計目的與動機44
4.1.1 CMOS接收機前端相關研究發展現況44
4.1.2傳統倍頻器架構47
4.2 K-band正交五倍頻器48
4.2.1正交五倍頻器電路原理48
4.2.2正交五倍頻器電路架構49
4.2.3電路模擬與測試58
4.3 77 GHz正交九倍頻器65
4.3.1正交九倍頻器電路原理65
4.3.2正交九倍頻器電路架構66
4.3.3電路模擬與測試69
4.3.4結果與討論73
第五章W頻段高功率耦合線之注入鎖定除頻器75
5.1 耦合線注入鎖定除頻器設計目的與動機75
5.1.1毫米波除頻器相關研究發展現況75
5.1.2近來發表之除頻器架構76
5.2 W頻段高功率耦合線之注入鎖定除頻器79
5.2.1 W頻段除頻器電路原理79
5.2.3電路模擬與測試82
第六章結論90
第七章未來研究91
參考文獻93

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