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系統識別號 U0026-1808201417050800
論文名稱(中文) 應用於多核心平台之高效率記憶體網路晶片系統
論文名稱(英文) A Memory-Efficient NoC System for Manycore Platform
校院名稱 成功大學
系所名稱(中) 電腦與通信工程研究所
系所名稱(英) Institute of Computer & Communication
學年度 102
學期 2
出版年 103
研究生(中文) 嚴健瑄
研究生(英文) Chien-Hsuan Yen
學號 q36014243
學位類別 碩士
語文別 英文
論文頁數 75頁
口試委員 指導教授-陳中和
口試委員-黃英哲
口試委員-徐慰中
口試委員-邱瀝毅
口試委員-賴伯承
中文關鍵字 動態隨機存取記憶體存取排程  網狀網路晶片  多層匯流排互聯  多核心系統  OpenCL框架 
英文關鍵字 DRAM access scheduling  Mesh Network-on-Chip  Multi-layer interconnection  Many-core system  OpenCL framework 
學科別分類
中文摘要 在現代的平行運算系統下,互聯(interconnection)和記憶體效能扮演很重要的角色。本論文中,我們評估一個基於ARM架構之多核心全系統平台在OpenCL框架中,執行由OpenCL卸載之內核程式時的運算效能。對於密集存取記憶體的OpenCL應用程式來說,多核心系統中每個核心所存取記憶體的時間在整體執行時間中佔極高的比例。儘管其應用程式平均的記憶體頻寬需求遠小於整體互聯系統及記憶體控制器所提供之實體頻寬,但爭奪記憶體所造成之額外負擔會隨著系統的規模變大而跟著提高,最終造成多核心系統之可擴展性大幅降低。
因此,我們首先開發一可配置之網狀網路晶片系統去提供比傳統匯流排互聯系統更高的互聯頻寬。但我們發現在執行密集存取記憶體的OpenCL應用程式時,網狀網路系統比互聯矩陣系統所提供之效能提升是很有限的。因此,我們整合了動態隨機存取記憶體存取排程之方法至該網路晶片系統以提升多達20%的記憶體存取效能。更重要的是,受益於網路晶片之封包交換特性,記憶體存取排程所帶來的效能提升會隨著系統的規模變大而愈加顯著,此特性恰巧符合了多核心系統之可擴展性的需求。因此,在多核心系統執行密集存取記憶體的OpenCL應用程式時,我們所提出的高效率記憶體網路晶片系統能有效提升多核心系統之可擴展性及記憶體存取效能。
英文摘要 Interconnection and memory performance plays an important role in the contemporary parallel computing system. In this thesis, we evaluate a full system ARM-based many-core platform under the OpenCL framework by offloading the kernel programs into the many-core processors. The memory access time dominates the total execution time for the many-core processors in the execution of the memory-intensive OpenCL application. Despite the fact that the physical bandwidth provided by the interconnection and memory controllers are very sufficient to the average bandwidth requirement of the applications, the memory contention overheads dramatically increase with the scaled system, resulting to the poor scalability of the many-core platform.
Therefore, we first develop a configurable mesh NoC system with higher interconnection bandwidth than the conventional bus-based on-chip interconnections. However, we find that the native NoC has only limited improvement compared to the interconnection matrix in the execution of the memory-intensive OpenCL application. Then, we integrate the DRAM memory access scheduling approach into the native NoC system to advance the overall memory performance up to 20%. More importantly, benefited by the packet-switch feature of the NoC, the performance improvement due to the memory access scheduling approach grows with the scaled system, matching the scalability requirement of the many-core system. In the execution of the memory-intensive OpenCL applications, the proposed the memory-efficient NoC system effectively upgrades the scalability and memory performance for the many-core platform.
論文目次 Chapter 1 - Introduction 1
1.1 Motivation 1
1.2 Contribution 2
1.3 Organization 3
Chapter 2 - Background 4
2.1 Network-on-Chip 4
2.1.1 Interconnection for Multiprocessor 4
2.1.2 Topology 6
2.1.3 Buffer Flow Control 8
2.1.4 Routing Protocol 10
2.1 DRAM Structure 12
2.2 OpenCL Framework 14
2.2.1 OpenCL Execution Model 15
2.2.2 OpenCL Memory Hierarchy 16
2.2.3 OpenCL Runtime System Architecture 17
Chapter 3 - Related work 19
3.1 Mesh NoC System 19
3.1.1 Priority-based Routing Protocol 19
3.1.1 Memory controller placement 20
3.1.2 Novel Research related to NoC 21
3.2 Memory Access Scheduling Scheme 22
Chapter 4 - Network-on-Chip Architecture 24
4.1 Overview of the NoC System 24
4.2 Routing Approach 25
4.2.1 Packet Format 25
4.2.2 Wormhole Flow Control 26
4.2.3 XY Laddering Routing 27
4.3 Detailed Descriptions of the Components in NoC System 28
4.3.1 Router Architecture 28
4.3.2 Hybrid Network Interface 30
4.3.3 Memory Controller 32
Chapter 5 - Many-Core Platform 33
5.1 Overview of the Many-Core Platform 33
5.2 Full System Simulation Platform for OpenCL 34
5.2.1 Work-item coalescing 36
5.2.2 OpenCL Memory Management 37
5.3 DRAM Access Scheduling Approach 39
Chapter 6 - Experiment 41
6.1 Experiment Environment 41
6.1.1 System Configuration 41
6.1.2 NoC Placement 43
6.2 Evaluation Metrics 45
6.2.1 Benchmark 45
6.2.2 Memory Access Flow 46
6.3 Performance Evaluation 48
6.3.1 Performance Bottleneck 48
6.3.2 Memory Access Scheduler 52
6.3.3 Scalability 55
6.4 Optimization 63
6.4.1 OpenCL Runtime 63
6.4.2 DDR3 65
6.4.3 Priority-Aging Hit-First Scheduling 67
Chapter 7 - Conclusion 70
References 72
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