進階搜尋


下載電子全文  
系統識別號 U0026-1708201511323900
論文名稱(中文) 金氧半微機電製程之多感測器讀取電路設計技術
論文名稱(英文) Design of Multi-Sensor Readout Circuit by Using CMOS MEMS Process
校院名稱 成功大學
系所名稱(中) 電機工程學系
系所名稱(英) Department of Electrical Engineering
學年度 103
學期 2
出版年 104
研究生(中文) 吳伯昌
研究生(英文) Po-Chang Wu
學號 N28951293
學位類別 博士
語文別 英文
論文頁數 94頁
口試委員 口試委員-許明華
口試委員-許孟烈
口試委員-李順裕
口試委員-張順志
口試委員-魏嘉玲
召集委員-唐經洲
指導教授-劉濱達
中文關鍵字 互補式金屬氧化物半導體微機電製程  誤差校正  低雜訊  低功耗 
英文關鍵字 CMOS MEMS  digital offset trimming  low-noise  low-power 
學科別分類
中文摘要 本論文驗證了具有感測器誤差校正功能低功耗/低雜訊之互補式金屬氧化物半導體微機電製程加速度器單晶片之設計技術。感測器因製程飄移所造成之靜態電容誤差往往比運動所產生之電容變化量來得大許多,若無適當的修正誤差則此一晶片便無法使用。本論文所提出的兩種校正機制具有低功耗、面積小之優勢,而量測結果也證明此一互補式金屬氧化物半導體微機電製程所製造之加速度器單晶片不論是在靈敏度、線性度、功率消耗或是輸出雜訊的表現均和商用產品具有相匹敵之性能。而利用極低電壓電路設計技巧所設計之0.6 伏特操作加速度器更具有0.2 毫瓦之低功耗,可偵測0.01 個重力加速度之變化,並具有一個14 位元輸出之三角積分類比/數位轉換器。最後本論文提出了一個以交換電容式架構為基礎之多感測器讀取電路,其以分時多工之機制可以提供電壓、電流、電阻和電容類型之轉換。利用此一通用型讀取電路,一個結合三軸加速度器、三軸磁力計以及ARM M0 微處理器之單晶片除了可以執行虛擬陀螺儀演算法,並提供了一個低功耗、低成本之虛擬陀螺儀解決方案。
英文摘要 This dissertation presents the design of low-power low-noise monolithic CMOS MEMS accelerometers using area-efficient digital offset trimming techniques to compensate for process variations caused by sensor capacitance mismatches. The consistent distributions of resonant frequency and sensitivity indicates that the wafer-level 0.18-μm CMOS MEMS process is suitable for integrated inertial sensors. The simulation and measurement results for the designed and fabricated chips show good linearity and noise performance, which are comparable to those seen with commercial products. A 0.6-V monolithic CMOS MEMS accelerometer design with automatic offset trimming capability is also demonstrated in this dissertation, in order to achieve further reductions in the power consumption of the sensor readout circuits. With only 0.2-mW power consumption, the readout circuit can detect smaller than 0.01 g acceleration with the digital output provided by a low-voltage 14-bit ΣΔ ADC. Finally, a multiplexed multi-sensor generic interface circuit which can support the voltage-to-voltage, currentto-voltage, resistance-to-voltage, and capacitance-to-voltage conversion requirements of different sensors is proposed. This feature makes multi-sensor SoC possible when integrating an embedded microprocessor and memory in the CMOS MEMS process. A test chip, which includes a three-axis CMOS MEMS accelerometer, the generic interface circuit, an incremental ΣΔ ADC, and an ARM M0 microprocessor, was fabricated. When combined with a three-axis magnetic sensor which needs some post processing after finishing all CMOS MEMS processes, this test chip can provide a low-power and low-cost three-axis virtual gyroscope with commercial applications.
論文目次 Abstract (Chinese) i
Abstract (English) iii
Acknowledgments v
Table of Contents vii
List of Tables ix
List of Figures x
Chapter 1. Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 CMOS MEMS Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Sensor Readout Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.1 Voltage to Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.2 Current to Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.3 Resistance to Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.4 Capacitance to Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4 Organization of the Dissertation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chapter 2. Monolithic Capacitive Accelerometer Design . . . . . . . . . . . . . . . . .13
2.1 Introduction of MEMS Accelerometers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 X-Axis Accelerometer Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.3 Readout Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.4 Sensor Mismatch and Automatic Offset Trimming Technique . . . . . . . . . . 27
2.5 Multi-Axis Accelerometer Readout Architecture . . . . . . . . . . . . . . . . . . . . . 30
2.6 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Chapter 3. Low-Voltage Low-Power Capacitive Accelerometer Design . . . . . . 42
3.1 Introduction of Low-Voltage Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.2 Fully-Differential Capacitive Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3 Low-Voltage OTA and CMP Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.4 Sensor Offset Trimming for Low-Voltage Capacitive Accelerometer . . . . . .55
3.5 Low-Voltage Sigma-Delta ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
3.6 Noise Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.7 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Chapter 4. Generic Sensor Readout Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
4.1 Introduction of Virtual Gyroscopes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
4.2 Z-Axis Accelerometer Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.3 Generic Readout Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
4.4 Incremental Sigma-Delta ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
4.5 SoC Implementation of a Virtual Gyroscope . . . . . . . . . . . . . . . . . . . . . . . . 81
4.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Chapter 5. Conclusions and Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
5.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
參考文獻 [1] G. Q. Zhang and A. van Roosmalen, More than Moore: Creating High Value Micro/Nanoelectronics Systems. New York: Springer, 2009.
[2] S. J. Sherman, W. K. Tsang, T. A. Core, R. S. Payne, D. E. Quinn, K. H. L. Chau, J. A. Farash, and S. K. Baum, “A low cost monolithic accelerometer,” in Proc. SPIE, Dec. 1992, pp. 501–504.
[3] J. H. Smith, S. Montague, J. J. Sniegowski, J. R. Murray, and P. J. McWhorter, “Embedded micromechanical devices for the monolithic integration of MEMS with CMOS,” in Proc. IEDM, Dec. 1995, pp. 609–612.
[4] A. A. Seshia, M. Palaniapan, T. A. Roessig, R. T. Howe, R. W. Gooch, T. R. Schimert, and S. Montague, “A vacuum packaged surface micromachined resonant accelerometer,” J. Microelectromech. Syst., vol. 11, no. 6, pp. 784–793, Dec. 2002.
[5] J. Yasaitis, M. Judy, T. Brosnihan, P. Garone, N. Pokrovskiy, D. Sniderman, S. Limb, R. Howe, B. Boser, M. Palaniapan, X. Jiang, and S. Bhave, “A modular process for integrating thick polysilicon MEMS devices with sub-micron CMOS,” in Proc. SPIE, Jan. 2003, pp. 145–154.
[6] S. A. Bhave, J. I. Seeger, X. Jiang, B. E. Boser, R. T. Howe, and J. Yasaitis, “An integrated, vertical-drive, in-plane-sense microgyroscope,” in IEEE Conf. Transducers, Jun. 2003, pp. 171–174.
[7] M. W. Jude, “Evolution of integrated inertial MEMS technology,” in Proc. Solid-State Sensor, Actuator and Microsystem Workshop, Jun. 2004, pp. 27–32.
[8] M. Offenberg, F. Larmer, B. Elsner, H. Munzel, and W. Riethmuller, “Novel process for a monolithic integrated accelerometer,” in Proc. Int. Conf. Solid-State Sensors and Actuators, Jun. 1995, pp. 589–592.
[9] J. M. Bustillo, G. K. Fedder, C. T. C. Nguyen, and R. T. Howe, Microsystem Technologies. New York: Springer, 1994.
[10] S. Sedky, A. Witvrouw, H. Bender, and K. Baert, “Experimental determination of the maximum post-process annealing temperature for standard CMOS wafers, ”IEEE Trans. Electron Devices, vol. 22, pp. 377–385, Feb. 2001.
[11] F. Y. Xiao, Y. Z. Juang, and C. F. Chiu, “CMOS-MEMS process,” Patent US 7435612B2, Jun. 13, 2008.
[12] S. H. Tseng, Y. J. Hung, Y. Z. Juang, and M. S. C. Lu, “A 5.8-GHz VCO with CMOS-compatible MEMS inductors,” Sensor. and Actuat. A: Physical, vol. 139, pp. 187–193, Sep. 2007.
[13] S. H. Tseng, C. L. Fang, P. C. Wu, Y. Z. Juang, and M. S. C. Lu, “A CMOS MEMS thermal sensor with high frequency output,” in Proc. IEEE Int. Conf. Sensors, Oct. 2008, pp. 387–390.
[14] S. H. Tseng, M. S. C. Lu, Y. J. Hung, and Y. Z. Juang, “High-Q CMOS MEMS resonator oscillator fabricated in a MPW batch process,” in Proc. Eurosensors XXIV, Sep. 2010, pp. 1360–1363.
[15] H. C. Li, S. H. Tseng, and M. S. C. Lu, “Study of CMOS micromachined selfoscillating loop utilizing a phase-locked loop driving circuit,” J. Micromech. Microeng., vol. 22, Apr. 2012.
[16] S. H. Tseng, M. S. C. Lu, P. C. Wu, Y. C. Teng, H. H. Tsai, and Y. Z. Juang, “Implementation of a monolithic capacitive accelerometer in a wafer-level 0.18 μm CMOS MEMS process,” J. Micromech. Microeng., vol. 22, Apr. 2012.
[17] S. Franco, Design with Operational Amplifiers and Analog Integrated Circuits. New York: McGraw-Hill, 2001.
[18] K. Funk, H. Emmerich, A. Schilp, M. Offenberg, R. Neul, and F. Larmer, “A surface micromachined silicon gyroscope using a thick polysilicon layer,” in Proc. IEEE Int. Conf. Micro Electro Mech. Syst., Jan. 1999, pp. 57–60.
[19] M. Lemkin and B. E. Boser, “A three-axis micromachined accelerometer with a CMOS position-sense interface and digital offset-trim electronics,” IEEE J. Solid-State Circuits, vol. 34, pp. 456–468, Apr. 1999.
[20] H. Luo, G. Zhang, L. R. Carley, and G. K. Fedder, “A post-CMOS micromachined lateral accelerometer,” IEEE J. Microelectromech. Syst., vol. 11, pp. 188–195, Jun. 2002.
[21] J. Wu, G. K. Fedder, and L. R. Carley, “A low-noise low-offset capacitive sensing amplifier for a 50-μg/rtHz monolithic CMOS MEMS accelerometer,” IEEE J. Solid-State Circuits, vol. 39, pp. 722–730, May 2004.
[22] H. Qu, D. Fang, and H. Xie, “A monolithic CMOS-MEMS 3-axis accelerometer with a low-noise, low-power dual-chopper amplifier,” IEEE Sensors J., vol. 8, pp. 1511–1518, Sep. 2008.
[23] A. Sadat, H. Qu, C. Yu, J. S. Yuan, and H. Xie, “Low-power CMOS wireless MEMS motion sensor for physiological activity monitoring,” IEEE Trans. Circuits Syst. I, vol. 52, pp. 2539–2551, Dec. 2005.
[24] Y. C. Liu, M. H. Tsai, T. L. Tang, and W. Fang, “Improvement of CMOS-MEMS accelerometer using post-CMOS selective electroplating technique,” in Proc. Int. Conf. Solid-State Sensor, Jun. 2011, pp. 1002–1005.
[25] R. F. Colton, “Piezoresistive accelerometer,” Patent US 4 430 895, Feb. 14, 1984.
[26] L. M. Roylance and J. A. Angell, “A batch-fabricated silicon accelerometer,” IEEE Trans. Electron Devices, vol. 26, pp. 1911–1917, Dec. 1979.
[27] A. M. Leung, J. Jones, E. Czyzewska, J. Chen, and B. Woods, “Micromachined accelerometer based on convection heat transfer,” in Proc. IEEE MEMS, Jan. 1998, pp. 627–630.
[28] W. Fang and J. A. Wickert, “Comments on measuring thin-film stresses using bi-layer micromachined beams,” J. Micromech. Microeng., vol. 5, pp. 276–281, 1995.
[29] V. P. Petkov and B. E. Boser, “A fourth-order ΣΔ interface for micromachined inertial sensors,” IEEE J. Solid-State Circuits, vol. 40, pp. 1602–1609, Aug. 2005.
[30] B. V. Amini and F. Ayazi, “A 2.5-V 14-bit CMOS SOI capacitive accelerometer,” IEEE J. Solid-State Circuits, vol. 39, pp. 2467–2476, Dec. 2004.
[31] L. He, Y. P. Xu, and M. Palaniapan, “A CMOS readout circuit for SOI resonant accelerometer with 4-μg bias stability and 20-μg/rtHz resolution,” IEEE J. Solid-State Circuits, vol. 43, pp. 1480–1490, Jun. 2008.
[32] C. T. Ko, S. H. Tseng, and M. S. C. Lu, “A CMOS micromachined capacitive tactile sensor with high frequency output,” IEEE J. Microelectromech. Syst., vol. 15, Dec. 2006.
[33] T. B. Gabrielson, “Mechanical-thermal noise in micromachined acoustic and vibration sensors,” IEEE Trans. Electron Devices, vol. 40, pp. 903–909, May 1993.
[34] B. E. Boser and R. T. Howe, “Surface micromachined accelerometers,” IEEE J. Solid-State Circuits, vol. 31, pp. 366–375, Mar. 1996.
[35] Y. Nemirovsky, I. Brouk, and C. Jakobson, “1/f noise in CMOS transistors for analog applications,” IEEE Trans. Electron Devices, vol. 48, pp. 921–927, May 2001.
[36] M. Paavola, M. Kämäräinen, J. A. M. Järvinen, M. Saukoski, M. Laiho, and K. A. I. Halonen, “A micropower interface ASIC for a capacitive 3-axis microaccelerometer,” IEEE J. Solid-State Circuits, vol. 42, pp. 2651–2665, Dec. 2007.
[37] M. Schipani, P. Bruschi, G. C. Tripoli, and T. Ungaretti, “A low power CMOS interface circuit for three-axis integrated accelerometers,” in Proc. Res. Microelectron. Electron. Conf., Jul. 2007, pp. 117–120.
[38] D. A. Johns and K. Martin, Analog Integrated Circuit Design. New Jersey: Wiley, 1997.
[39] C. M. Sun, M. H. Tsai, Y. C. Liu, and W. Fang, “Implementation of a monolithic single proof-mass tri-axis accelerometer using CMOS-MEMS technique,” IEEE Trans. Electron Devices, vol. 57, pp. 921–927, Jul. 2010.
[40] ADXL337 Data Sheet, Analog Device Inc, CA, United States.
[41] MMA6361L Data Sheet, Freescale Semiconductor Inc, Texas, United States.
[42] E. A. Vittoz, “Future of analog in the VLSI environment,” in Proc. ISCAS, May 1990, pp. 1372–1375.
[43] P. R. Kinget, “Device mismatch and tradeoffs in the design of analog circuits,” IEEE J. Solid-State Circuits, vol. 40, pp. 1212–1224, Jun. 2002.
[44] K. Bult, “Analog design in deep sub-micron CMOS,” in Proc. ESSCIRC, Sep. 2000, pp. 126–132.
[45] Q. Huang, “Low voltage and low power aspects of data converter design,” in Proc. ESSCIRC, Sep. 2004, pp. 29–35.
[46] A. P. Chandrakasan, D. C. Daly, J. Kwong, and Y. K. Ramadass, “Next generation micro-power systems,” in Proc. IEEE Symp. VLSI Circuits, Jun. 2008, pp. 2–5.
[47] K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, “CMOS smart sensor for monitoring the quality of perishables,” IEEE J. Solid-State Circuits, vol. 42, pp. 798–803, Apr. 2007.
[48] T. Kleeburg, J. Loo, N. J. Guilar, E. Fong, and R. Amirtharajah, “Ultra-lowvoltage circuits for sensor applications powered by free-space optics,” in ISSCC Dig. Tech. Papers, Feb. 2009.
[49] M. J. Chen, J. S. Ho, T. H. Huang, C. H. Yang, Y. N. Jou, and T. Wu, “Backgate forward bias method for low-voltage CMOS digital circuits,” IEEE Trans. Electron Devices, vol. 43, pp. 904–910, Jun. 1996.
[50] B. J. Blalock, P. E. Allen, and G. Rincon-Mora, “Designing 1-V op amps using standard digital CMOS technology,” IEEE Trans. Circuits Syst. II, vol. 45, pp. 769–780, Jul. 1998.
[51] T. Lehmann and M. Cassia, “1-V power supply CMOS cascode amplifier,” IEEE J. Solid-State Circuits, vol. 36, pp. 1082–1086, Jul. 2001.
[52] T. Stockstad and H. Yoshizawa, “A 0.9-V 0.5-μA rail-to-rail CMOS operational amplifier,” IEEE J. Solid-State Circuits, vol. 37, pp. 286–292, Mar. 2002.
[53] S. Chatterjee, Y. Tsividis, and P. Kinget, “0.5-V analog circuit techniques and their application in OTA and filter design,” IEEE J. Solid-State Circuits, vol. 40, pp. 2373–2387, Dec. 2005.
[54] T. Kunikiyo, K. Mitsui, M. Fujinaga, T. Uchida, and N. Kotani, “Reverse shortchannel effect due to lateral diffusion of point-defect induced by source/drain ion implantation,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 37, pp. 507–514, Apr. 1994.
[55] T. Kobayashi and T. Sakurai, “Self-adjusting threshold-voltage scheme (SATS) for low-voltage high-speed operation,” in Proc. CICC, May 1994, pp. 271–274.
[56] V. R. von Kaenel, M. D. Pardoen, E. Dijkstra, and E. A. Vittoz, “Automatic adjustment of threshold and supply voltages for minimum power consumption in CMOS digital circuits,” in IEEE Symp. Low Power Electron. Dig. Tech. Papers, Oct. 1994, pp. 78–79.
[57] J. W. Tschanz, J. T. Kao, S. G. Narendra, R. Nair, D. A. Antoniadis, A. P. Chandrakasan, and V. De, “Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage,” IEEE J. Solid-State Circuits, vol. 37, pp. 1396–1402, Nov. 2002.
[58] J. T. Kao, M. Miyazaki, and A. P. Chandrakasan, “A 175-mV multiply-accumulate unit using an adaptive supply voltage and body bias architecture,” IEEE J. Solid-State Circuits, vol. 37, pp. 1545–1554, Nov. 2002.
[59] S. Narendra, J. Tschanz, J. Hofsheier, B. Bloechel, S. Vangal, Y. Hoskote, S. Tang, D. Somasekhar, A. Keshavarzi, V. Erraguntla, G. Dermer, N. Borkar, S. Borkar, and V. De, “Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique,” in ISSCC Dig. Tech. Papers, Feb. 2004, pp. 156–157.
[60] B. E. Boser and B. A. Wooley, “The design of sigma-delta Modulation analogto-digital converters,” IEEE J. Solid-State Circuits, vol. 23, pp. 1298–1308, Dec. 1988.
[61] G. Yin and W. Sansen, “A high-frequency and high-resolution fourth order ΣΔ A/D converter in BiCMOS technology,” IEEE J. Solid-State Circuits, vol. 29, pp. 857–865, Aug. 1994.
[62] A. Marques, V. Peluso, M. Steyaert, and W. Sansen, “Optimal parameters for cascade ΣΔ modulators,” in Proc. ISCAS, Jun. 1997, pp. 61–64.
[63] F. Medeiro, B. Pérez-Verdú, J. M. de la Rosa, and A. Rodríguez-Vázquez, “Fourthorder cascade ΣΔ modulators: a comparative study,” IEEE Trans. Circuits Syst. I, vol. 45, pp. 1041–1051, Oct. 1998.
[64] ADXL335 Data Sheet, Analog Device Inc, CA, United States.
[65] LIS331EB Data Sheet, STMicroelectronics Inc, Geneva, Swiss.
[66] A. Selvakumar, F. Ayazi, and K. Najafi, “A high-sensitivity z-axis capacitive silicon microaccelerometer with a torsional suspension,” IEEE J. Microelectromech. Syst., vol. 7, pp. 192–200, Jun. 1998.
[67] S. H. Tseng, P. C. Wu, H. H. Tsai, and Y. Z. Juang, “Monolithic z-axis CMOS MEMS accelerometer,” Microelectronic Engineering, vol. 119, pp. 178–182, May 2014.
[68] S. Timoshenko, Theory of Elasticity. New York: McGraw-Hill, 1970.
[69] J. Markus, J. Silva, and G. C. Temes, “Theory and applications of incremental ΣΔ converters,” IEEE Trans. Circuits Syst. I, vol. 51, pp. 678–690, Apr. 2004.
[70] J. Robert and P. Deval, “A second-order high-resolution incremental A/D converter with Offset and charge injection compensation,” IEEE J. Solid-State Circuits, vol. 23, pp. 736–741, Jun. 1988.
[71] G. C. Temes, Y. Wang, W. Yu, and J. Markus, “Incremental data converters,” in Proc. MTNS, Jul. 2010, pp. 715–721.
[72] T. C. Caldwell and D. A. Johns, “Incremental data converters at low oversampling ratios,” IEEE Trans. Circuits Syst. I, vol. 57, pp. 1525–1537, Jul. 2010.
[73] V. Quiquempoix, P. Deval, A. Barreto, G. Bellini, J. Markus, J. Silva, and G. Temes, “A low-power 22-bit incremental ADC,” IEEE J. Solid-State Circuits, vol. 41, pp. 1562–1571, Jul. 2006.
論文全文使用權限
  • 同意授權校內瀏覽/列印電子全文服務,於2018-08-27起公開。
  • 同意授權校外瀏覽/列印電子全文服務,於2018-08-27起公開。


  • 如您有疑問,請聯絡圖書館
    聯絡電話:(06)2757575#65773
    聯絡E-mail:etds@email.ncku.edu.tw