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系統識別號 U0026-1608201715445200
論文名稱(中文) 應用於智慧工業之可攜式虛擬處理器系統
論文名稱(英文) Portable Virtual Processor System for Smart Industry
校院名稱 成功大學
系所名稱(中) 電腦與通信工程研究所
系所名稱(英) Institute of Computer & Communication
學年度 105
學期 2
出版年 106
研究生(中文) 許士杰
研究生(英文) Shih-Chieh Hsu
學號 Q36044183
學位類別 碩士
語文別 中文
論文頁數 65頁
口試委員 指導教授-陳中和
口試委員-陳培殷
口試委員-蘇文鈺
召集委員-蕭勝夫
口試委員-黃穎聰
中文關鍵字 數位訊號處理器  嵌入式系統  指令集模擬器  RISC-V  智慧工業 
英文關鍵字 Digital Signal Processor (DSP)  Embedded System  Instruction Set Simulator (ISS)  RISC-V  Smart Industry 
學科別分類
中文摘要 自從工業4.0之興起,快速開發新一代產品以滿足上市時間的最終期限是非常重要的。開發商需要評估其需求而選擇匹配之硬件設備,如數位訊號處理器(DSP)、嵌入式系統硬體開發板等。舉例來說,機器手臂被導入自動化生產作業流程時,為了控制機械手臂、監控機械手臂之健康狀況、數據處理、數據接收與傳送,開發商必須選擇一個高性能開發板或者透過通用型電腦來處理多個任務或採用即時作業系統,然而,不論是在何種工業領域中,快速移植應用程式甚至是移植作業系統到不同的硬體平台上是非常不容易的而且需要很多時間去移植。
一個平台上為了支援應用程式可移植性,通常會掛載一個虛擬機器,像是JVM、BlueStacks…等,然而由於工業上使用嵌入式系統開發之硬體平台記憶體資源有限,必須要考慮到其記憶體限制而選擇相對應之虛擬機器。在虛擬機器上應提供軟體除錯功能以利開發者除錯。另一方面,在工業的自動控制領域中,控制器是不可或缺的角色,而市面上所使用的運動控制卡通常以腳本語言進行撰寫並控制工業應用之嵌入式硬體,若是此虛擬機器能提供彈性增加指令的話,而能將每一個指令對應到一個控制演算法,虛擬機器也能如市面上直譯方式將指令轉為相對應之動作,豐富了虛擬機器於工業上之應用。
在本論文中,我們提出了應用於智慧工業之可攜式虛擬處理器系統,虛擬處理器系統是一個C語言撰寫之RISC-V指令集模擬器,而在DSP28335之執行檔大小包含支援GDB的模組僅需23.65 KB而在host x86上僅需43.4 KB,比RISC-V官方提供之指令集模擬器小了約10倍左右。本論文提出之虛擬處理器系統支援GDB遠端除錯功能,除了支援一般TCP/IP溝通方式外,亦提供了使用串行通信 (Serial Communication) 之GDB除錯方式,而考慮到可能會有人透過除錯路徑進行非法記憶體存取,虛擬處理器系統提供了記憶體保護機制來防止這種情況。另一方面,虛擬處理器系統可以擴增指令集來符合工業應用,像是應用於運動控制卡。最後,為了評估虛擬處理器系統,我們選擇DSP28335以及host x86平台作為我們的評估平台,在DSP28335執行效能約0.23 MIPS,而在host x86平台執行效能約40-60 MIPS,並使用了Mibench 作為平台驗證之testbench,另外,我們將FreeRTOS修改並成功運行在本論文提出之虛擬處理器系統上。
英文摘要 This thesis develops a portable, lightweight, secure and GDB-supported virtual processor system for smart industry. The virtual processor system mimics the behavior of a RISC-V processor. RISC-V is an open instruction set architecture and extensible for implementing customized instructions. In this thesis, we implement the customized instructions for calling the native library on the digital signal processor (DSP). The virtual processor system remaps the memory address between the host device and the RISC-V application. When an exception or an interrupt occurs, the virtual processor system will call the trap handler or interrup handler and perform the interrupt sub routine (ISR). The developer can use GDB to debug the RISC-V application through the network or the serial communication interface. To avoid illegal memory access, the virtual processor system also provides the memory protection mechanism.
We evaluate the virtual processor system on the DSP28335 and the host x86 platform with the FreeRTOS as well as the MiBench. The virtual processor system takes 23.65 KB on DSP28335 and 43.4 KB on host x86 platform. The performance on host x86 platform is about 40-60 MIPS and 0.23 MIPS on DSP28335.
論文目次 摘要 I
SUMMARY II
INTRODUCTION II
SYSTEM DESIGN AND IMPLEMENTATION III
EXPERIMENT RESULT IV
CONCLUSION V
誌謝 VI
目錄 VII
表目錄 X
圖目錄 XI
Chapter 1. 序論 1
1.1 研究動機 1
1.2 研究貢獻 4
1.3 論文架構 5
Chapter 2. 背景知識與相關研究 6
2.1 虛擬機器 6
2.2 指令集模擬器 8
2.3 RISC-V 10
2.3.1 RISC-V ISA 11
2.3.2 RISC-V 指令集模擬器 14
2.3.3 RISC-V GNU Toolchain 15
2.4 GNU Debugger (GDB) 16
2.4.1 Introduction to GDB 16
2.4.2 Remote Serial Protocol 16
2.5 相關研究 18
Chapter 3. 可攜式虛擬處理器系統 20
3.1 RISC-V 指令集模擬器 20
3.1.1 RISC-V 處理器 22
3.1.2 Embedded MMU 24
3.1.3 Trap Handler 29
3.1.4 Interrupt Handler 31
3.1.5 Embedded gdbstub 33
3.2 虛擬處理器系統之軟體開發套件 37
Chapter 4. 系統移植方法 39
4.1 RISC-V程式設定 42
4.2 虛擬處理器系統設定 43
4.3 移植動作 45
4.4 FreeRTOS 配置 45
4.4.1 Example Tasks Initialization 47
Chapter 5. 實驗結果 50
5.1 實驗環境 50
5.2 模擬結果 53
Chapter 6. 結論 62
參考文獻 63
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