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系統識別號 U0026-1602201114504700
論文名稱(中文) 軟硬體協同模擬架構效能加速之設計與分析
論文名稱(英文) An Efficient ESL Co-Simulation Platform using Shared-Memory Communication Scheme
校院名稱 成功大學
系所名稱(中) 電機工程學系專班
系所名稱(英) Department of Electrical Engineering (on the job class)
學年度 99
學期 1
出版年 100
研究生(中文) 楊卓銘
研究生(英文) Cho-Ming Yang
學號 n2796121
學位類別 碩士
語文別 中文
論文頁數 91頁
口試委員 指導教授-陳中和
口試委員-侯廷偉
口試委員-蘇文鈺
口試委員-黃俊岳
中文關鍵字 none 
英文關鍵字 ESL  Parallel  Shared Memory  Simulation  SystemC 
學科別分類
中文摘要 目前在硬體設計的範疇中,整個設計的流程由於產品更新速度的大幅增加,設計及驗證的時間越來越具急迫性。因此,近年來軟硬體協同設計的概念越來越被重視,並且也可由這個方式達到軟硬體同時進行設計及驗證的功能。
本篇論文基於在一個包含QEMU及CoWare的協同設計平台上[16],對於整體模擬的架構做分析及效能的改善。這個架構是由QEMU端模擬ARM處理器,並以Socket介面連接至模擬硬體的CoWare端以達成軟硬體協同設計模擬。
經由分析後發現由於模擬的架構會大量使用到Socket間的溝通,造成在Socket介面部分由於傳輸時間過長而增加模擬時的負擔,因此本論文提出了以Shared Memory 介面取代 Socket介面做為軟硬體模擬間的溝通方式,增加整體模擬的效率平均可達到1.46倍,其中對於資料量最大的Benchmark “Bunny”速度可加快到1.6倍。
而對於CoWare端的ESL層級模擬,由於SystemC只支援single process的執行,因此本論文也提出一個約會程序平行模擬(Rendezvous Parallel Simulation)的概念,將硬體端負載較重的部分抽離出原本單一程序模擬的環境,並以外部Process的方式附加到原本的模擬平台上,再利用Shared Memory做為中介層,讓各個模擬程序的資料可以互相流通,使硬體模擬部份可以在原本應用CoWare及SystemC的架構中提升整個硬體模擬平台的模擬速度。對於產生一張3D圖像來說,這個方法可以改善模擬速度平均達到約3.6倍的速度。
英文摘要 Hardware-software co-designs are getting more and more important for complex SoC development. This thesis anylyzes a hybrid simulation system and improves the efficiency of the simulation based on a platform using QEMU and CoWare tool[16]. The co-simulation system includes QEMU simulating the ARM processor, and the CoWare tool simulating hardware with socket connecting both sides.
After analyzing the simulation structure, we find that the current simulation systrem has massive socket communications, and this significantly increases simulation overhead due to the long communication time of sockets. Therefore, this thesis presents a communication method to replace socket with shared memory to improve the simulation efficiency up to 1.46 times. For benchmark Bunny, the improvement is up to 1.6 times.
For ESL level simulation with CoWare, because SystemC library only supports single thread execution, this thesis also introduces a concept that extracts part of the heavy workload in hardware simulation and moves this part of simulation to a process outside of the CoWare platform. Shared memory is used to be the interface that exchanges the data for the two simulation processes. The hardware simulation with CoWare can then have better simulation efficiency, and the hardware simulation platform can speed up to about 3.6 times in average.
論文目次 目錄
第1章 序論 11
1.1 Motivation 11
1.2 Contribution 12
1.3 Organization of Thesis 12
第2章 背景知識與相關研究 13
2.1 Electronics System Level Design 13
2.1.1 Simulation Accuracy 14
2.1.2 Transaction Level Modeling & Event Driven Modeling 16
2.1.3 SystemC 17
2.1.4 CoWare Platform Architect & ARM SoC Designer 18
2.1.5 Hardware-Software Co-design 19
2.1.6 Hardware-Software Partition 20
2.2 Full system simulation platform 22
2.2.1 QEMU-SystemC 23
2.2.2 QEMU-CoWare 24
2.3 CPU Instruction Set Simulator 25
2.3.1 Interpretive simulation 26
2.3.2 Compiled Simulation 27
2.3.3 Dynamic Compiled Simulation 28
2.3.4 Processor Emulator 29
2.3.5 Translation Block 32
2.3.6 QEMU Execution Flow 33
2.3.7 Peripheral Model 36
2.3.8 Interrupt Handler 36
2.4 Linux Device Driver 37
2.4.1 Classes of devices and modules 38
2.4.2 I/O ports and I/O memory 39
2.5 Introduction of 3D Computer Graphics 40
第3章 軟硬體協同模擬的加速原理及設計 44
3.1 Simulation Time Issue 44
3.2 Communication Interface 46
3.3 Simulation Platform Improvement 50
3.3.1 Tiled-Based GPU Structure 51
3.3.2 Geometry Engine 52
3.3.3 Rasterizer Engine 56
3.3.4 Application Programming Interface 58
3.3.5 GPU Hardware Analysis 63
第4章 實驗環境與實驗結果 75
4.1 Simulation Environment 75
4.1.1 Simulation Framework 76
4.1.2 Benchmarks 77
4.2 Communication Interface Comparison 78
4.3 Rendezvous Parallel Simulation 83
第5章 結論與未來展望 88
5.1 結論 88
5.2 未來展望 89
參考文獻 90

參考文獻 參考文獻

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