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系統識別號 U0026-1602201114343600
論文名稱(中文) 使用強迫式錯誤傳遞方法之混合式軟體自我測試方案
論文名稱(英文) A Hybrid SBST Methodology through Forced Fault Propagation
校院名稱 成功大學
系所名稱(中) 電機工程學系碩博士班
系所名稱(英) Department of Electrical Engineering
學年度 99
學期 1
出版年 100
研究生(中文) 郭書侖
研究生(英文) Shu-Lun Kuo
學號 v3697103
學位類別 碩士
語文別 中文
論文頁數 70頁
口試委員 指導教授-陳中和
口試委員-侯廷偉
口試委員-蘇文鈺
口試委員-黃俊岳
中文關鍵字 軟體式自我測試  數位訊號處理器  製造測試 
英文關鍵字 DSP testing  manufacturing testing  software-based self-testing 
學科別分類
中文摘要 隨著多媒體資訊的快速發展,對於數位訊號處理器(Digital Signal Processor, DSP)的需求也日益增加。如何確保數位訊號處理器的功能正常則是個重要的議題。製造測試為晶片下線後的重要環節,對晶片功能是否正常做最後的把關。傳統的Scan-based與BIST的測試方案,都需要內建測試電路來進行測試工作,對此將造成整體面積的增加。而軟體式自我測試方案(Software-Based Self-Testing, SBST)則不需增加額外的測試電路,且有助於電路最佳化的設計,同時也能夠讓處理器正常執行速度(at-speed)下進行測試。

本篇論文提出一套混合式軟體自我測試方案(SBST),並對管線設計的DSP進行測試。而測試程式的開發則結合隨機性(Random)與自定性(Deterministic)兩種測試方案,來達到較高的錯誤涵蓋率(Fault coverage)。隨機測試程式的發展是透過硬體架構與指令集的分析,並建構Basic block作為隨機測試程式的發展基礎,以隨機方式產生不同資料路徑的指令來測試DSP的線路錯誤。而自定性測試程式的發展則是透過強迫式的錯誤資訊傳遞方法,讓有條件限制的ATPG(Automatic test pattern generation)所產生的測試向量能夠有效率的執行。最後將本篇論文所提出的混合式軟體自我測試方法實現於DSP的測試,可達到95.46%的錯誤涵蓋率。
英文摘要 With the highly developed multimedia information, the demand for Digital Signal Processor (DSP) is increasing. How to test the correctness of the functions of a DSP chip becomes an important issue. Manufacturing test for the functionality of the chip is an important stage after the tape-out of the chip. Both traditional scan-based and built-in self-testing (BIST) testing methodologies require built-in testing circuit to support testing procedure, which leads to an increase in overall area. However, software-based self-testing (SBST) not only needs no additional testing circuits, but also is helpful for optimizing the circuit design and allows the testing to be performed at the normal processor execution speed.

In this thesis, we propose a hybrid SBST methodology, and apply it to test a pipeline DSP. The development of test program combines both random and deterministic schemes to achieve high fault coverage. The random test program is developed by analyzing the hardware architecture and the instruction set, and by building basic blocks as the basis of the random testing program. The deterministic test program is developed by forcing fault propagation, so that the constrained test vectors generated by the ATPG tool can be executed efficiently. Furthermore, the hybrid SBST we propose is applied to DSP processors and has achieved 95.46% in processor core fault coverage.
論文目次 目錄
摘要 I
Abstract II
誌謝 III
目錄 IV
表目錄 VII
圖目錄 IX
第一章 Introduction 1
1-1 Motivation 1
1-2 Contribution 2
1-3 Organization 2
第二章 Background and Related Work 3
2-1 Testing overview 3
2-1-1 Single stuck-at fault model 4
2-1-2 Scan-based Testing 5
2-1-3 Hardware-based Testing 7
2-1-4 Software-based Testing 8
2-2 Related Work 11
第三章 DSP架構介紹 13
3-1 TI-Compatible DSP 13
3-1-1 TI-Compatible DSP硬體架構 14
3-1-2 TI-Compatible DSP指令功能分類 16
3-1-3 暫存器架構 17
3-1-4 定址模式 23
3-2 SCREAM DSP16 28
3-2-1 SCREAM DSP16硬體架構 28
3-2-2 SCREAM DSP16指令功能分類 29
3-2-3 暫存器架構 30
3-2-4 定址模式 31
3-3 Summary 33
第四章 Methodology 34
4-1 所提出的軟體式自我測試方案 34
4-2 Test program generation 38
4-2-1 Architecture analysis 38
4-2-2 Random test program generation 40
4-2-3 Deterministic test program generation 43
4-2-4 Fundamental IP測試程式開發方法 46
4-2-5 Module based測試程式開發方法 49
4-3 Fault simulation 51
4-3-1 Test shell module 51
4-3-2 Signal capture 52
4-4 Summary 53
第五章 Experimental result 54
5-1 Basic block數量與錯誤涵蓋率的成長 54
5-2 Synthesis Case 1:TSMC0.18um , 50MHZ 56
5-3 Synthesis Case 2:TSMC 0.13 um , 50MHZ 59
5-4 SBST測試方案與Full scan比較 62
5-5 SBST測試方案的應用與限制 63
5-6 SBST測試方案與其他學者測試方案比較 64
5-7 Summary 65
第六章 Conclusion and future work 66
6-1 Conclusion 66
6-2 Future work 66
參考資料 67

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