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系統識別號 U0026-1601201223080000
論文名稱(中文) 化學機械研磨應用於先進內連線缺陷與可靠度之研究
論文名稱(英文) Defect and Reliability Studies of Chemical Mechanical Polish Applications in Advanced Interconnects
校院名稱 成功大學
系所名稱(中) 微電子工程研究所碩博士班
系所名稱(英) Institute of Microelectronics
學年度 100
學期 1
出版年 101
研究生(中文) 許嘉麟
研究生(英文) Chia-Lin Hsu
學號 q1896114
學位類別 博士
語文別 英文
論文頁數 163頁
口試委員 口試委員-方炎坤
口試委員-王水進
召集委員-楊建倫
口試委員-蔡騰群
口試委員-蔡明蒔
指導教授-彭洞清
中文關鍵字 分子層沉積鎢  二硼烷  銅化學機械研磨  銅金屬導線  銅表面粗糙度  缺陷  直接研磨  電化學  電子遷移  失效模式  電鍍鏽蝕腐蝕  多孔性的低介電常數材料  化學機械研磨後清潔  時間取決之介電崩潰  鎢化學機械研磨 
英文關鍵字 ALD W  B2H6  Cu CMP  Cu interconnect  Cu roughness  defect  direct polish  electrochemistry  electro-migration  EM  failure mode  galvanic corrosion  porous low-k  post-CMP clean  time-dependent dielectric breakdown  TDDB  WCMP 
學科別分類
中文摘要 本論文主要研究主題,是針對金屬化學機械研磨應用於45奈米至28奈米的先進製程可能遭遇的各種缺陷及可靠度的問題。內容主要分為二大主題。其中第一主題中,探討當使用的分子層沉積法當成鎢成核層(nucleation layer),以形成低阻值的鎢插塞(W plug)時,所造成鎢金屬化學機械研磨中的鎢腐蝕,其電化學行為的探討。第二主題,主要則在探討先進半導體銅金屬導線製程當中,為有效降低介電層的介電常數(k value),所導入多孔性的低介電常數材料,其引起的與銅化學機械研磨相關的各種缺陷及可靠度的問題。
首先於第一主題中,在28奈米的製程開發中,發現鎢插塞製程裡於鎢接觸窗(contact)的阻障層與鎢的主沉機層中於表面會形成鎢的凹陷。本研究利用電化學的動電位的極化掃瞄(potentiodynamic polarization scan)探討於鎢金屬化學機械研磨的研磨液中,過氧化氫(H2O2) 的濃度對於以二硼烷(diborane, B2H6) 進行還原反應之分子層沉積法所形成之鎢成核層與阻障層氮化鈦(TiN)之間電位差的影響。進而瞭解到在有過氧化氫的研磨液環境中,於此介面有相對有較高的電位差,導致有高的傾向會發生電鍍鏽蝕腐蝕(galvanic corrosion) 。當過氧化氫的濃度進一步增加時,此電位差並不會進一步增加,但是腐蝕電流密度則會隨著過氧化氫的濃度增加而正比的增加。由傳輸電子顯微鏡(TEM)的影像顯示,鎢分子層沉積之成核層凹陷的深度亦與過氧化氫的濃度成正比,此結果驗證了以上電化學的測試結果。最後,鎢分子層沉積之成核層不同的前處理及後處理與成核層凹陷深度的關係亦被調查。
其次於第二主題中,先進半導體銅金屬導線製程與銅化學機械研磨相關的各種的問題。可進一步區分成缺陷及可靠度的研究兩部份。有關缺陷部分的研究,於先進製程中,因為線寬的縮減及因導入多孔性的低介電常數材料,其材料性質不利於銅化學機械研磨,當要降低有效的介電常數而進行所謂直接研磨(direct polish)時,衍生出一些新的缺陷,為達到高的量產良率,此些缺陷就需被研究探討並解決。其一為火山口缺陷(Crater Defect, ring shape metal bridge),此種缺陷被鑑定為前層的銅化學機械研磨中,氧化鋁(Al2O3)研磨粒子(abrasive)的殘留所造成,當突出的殘留物會造成之後的光阻鍍膜的厚度不均勻,使得後續蝕刻的電漿對下層的多孔性的低介電常數材料層造成收縮,並進而於接下來的銅化學機械研磨中,產生類似火山口的金屬殘留物,以膠態的二氧化矽研磨粒的研磨液可有效的改善此缺陷。其二為剝離缺陷(Peeling defect)。多孔性的低介電常數介電層之上常會以電漿做處理以改善與其上的薄膜之間黏附度。然當研磨至此介面時,即易形成剝離缺陷。如能進一步研磨致下方未被電漿處理過的介電層,此缺陷即可被避免。其三為高銅表面粗糙度缺陷(Cu roughness defect) ,此缺陷可能造成其後的黃光圖案形變,及介層窗的斷路 (via open) 而影響到量產良率。利用研磨後清潔液的濃度及清潔時間的最佳化,即可達到好的銅表面粗糙度。經過此些改善,量率的提升亦被驗證。
而有關先進製程銅化學機械研磨影響可靠度部分的研究,本論文探討銅化學機械研磨後的清潔時間對時間取決之介電崩潰(time dependent dielectric breakdown, TDDB)及電子遷移(electro-migration, EM)的影響。當清潔時間太短,遺留在多孔性的低介電常數介電層表面的銅殘留分子或離子,將嚴重的降低TDDB的生命期(lifetime)。相反的,過長的清潔時間雖能降低遺留在多孔性的低介電常數介電層表面的銅殘留分子或離子濃度,卻也同時造成高的銅表面粗糙度進而縮短了TDDB的生命期。而在對電子遷移的影響方面,稍高的銅表面粗糙度可以增進介電阻障層與銅表面的附著度,因而增長了電子遷移的故障均時(mean time to failure)。然而更進一步的高的銅表面粗糙度,於較深的區域,反而會形成與阻障層之間的一個裂縫。此裂縫會降低附著強度,並且成為電子遷移的起始處,而造成電子遷移生命期的嚴重退化。
最後本論文探討銅化學機械研磨直接研磨多孔性的低介電常數材料的製程中,時間取決之介電崩潰的失效模式。多孔性的低介電常數材料與傳統二氧化矽玻璃(silica glass)及非多孔性的低介電常數材料對時間取決之介電崩潰不同的是,其不只對導線的幾何形狀敏感,亦對製作過程當中的工程手法相關。於此論文中,我們歸納出三種多孔性的低介電常數材料時間取決之介電崩潰的失效模式。並分別對其相關的機制及對製程的敏感度做探討。
英文摘要 This dissertation mainly investigates the defect and reliability issues when the metal chemical mechanical polish (CMP) applied in the advanced interconnect for 45 nanometer generation and beyond. The contents are primary divided into two major topics. In the first topic, the study is focused on the electrochemical behaviors of Tungsten (W) corrosion in WCMP when W atomic layer deposition was introduced to form low resistive contact in the 28 nm technology node. In the second topic, the investigations focus on the Copper (Cu) CMP related defect and reliability issues in the direct polish scheme for the porous type low k materials which is introduced to reduce the effective k value.
In the first topic, Tungsten missing was observed at the interface between contact barrier layer and W in the 28nm node contact process. The potentiodynamic polarization scans showed that H2O2 in the W chemical-mechanical-polishing slurry increased the potential difference between the diborane (B2H6) reduced atomic layer deposited (ALD) W and TiN, suggesting that there is a high tendency for galvanic corrosion to occur. This potential difference kept constant, but the corrosion current density increased when the H2O2 concentration increased. The TEM image showed the depth of ALD W missing is proportional to the H2O2 concentration, which agrees with the electrochemical testing results. ALD W films with various pre- and post-treatments and their correlations with the degree of W missing were also investigated.
In the second topic, the related issues of Cu CMP application in the advanced BEOL Cu interconnects were studied. The topic is further separated into two parts, defects and reliabilities. In the defect studies, the specific 45nm direct polish related defects and their effects were investigated in order to achieve the high yield manufacturing feasibility of direct polish to porous low-k dielectric film. Three defect types were investigated. 1. Crater defect (ring shape metal bridge): Crater defect was identified caused by abrasive residue in the pre-metal layer polish. Polished with colloidal silica based Cu slurry could suppress this defect efficiently. 2. Peeling defect: The plasma treatment on porous low-k (pLK) layer improved the adhesion. However, it induced peeling when polish stop at this treated interface. It could be removed if further polish to intact ULK film. 3. High Cu roughness defect: High Cu roughness possibly induced both pattern missing and via open in the following metal layer and suffered the yields. By optimizing clean chemical concentration and clean time satisfied the needs of Cu roughness. Yield improvement proved the manufacturing feasibility of pLK direct polish technology.
In the reliability studies, the influences of post Cu chemical-mechanical-polish cleaning time on time dependent dielectric breakdown (TDDB) and electro-migration (EM) are reported. Cu residue remaining on the porous-low-k (pLK) film surface between Cu lines is a significant factor in TDDB lifetime when the cleaning time is short. In contrast, a longer cleaning time generates low Cu residue on the pLK surface but results in high Cu surface roughness, which leads to TDDB degradation. For EM performance, slightly higher roughness could improve the adhesion of the dielectric barrier layer to the Cu surface, thus increasing its mean time to failure. Further increases in Cu surface roughness, caused by extended cleaning, may generate a seam in the dielectric barrier layer at the deep-recessed trench area. The seam degrades the adhesion strength of the dielectric barrier to Cu and is the initiating site of Cu migration. As a result, it significantly degrades the EM lifetime.
Finally, the TDDB failure modes of Cu CMP direct polish to porous-low-k materials are investigated. Because of the ULK characteristics and the minimized feature size, the TDDB failure mode behaves different from silica glass or non-porous-low-k film. It is not only sensitive to geometries but also very sensitive to the engineering in the fabrication process. In this study, we identified three TDDB failure modes, Cu protrusion from trench top interface, sidewall, and bottom corner, in the direct polished pLK scheme. In addition, on the basis of those failure modes, the related mechanisms in conjunction with the sensitivity to the processes are reported as well.
論文目次 Abstract (in Chinese) (II)
Abstract (in English) (V)
Contents (IX)
Figure Captions (XIII)

Chapter 1 Introduction
§ 1.1 Motivation 1
§ 1.2 Thesis Organization 3
§ References 5

Chapter 2 Theory, Literature reviews and Motivations
§ 2.1 Requirements for Planarization 6
2.1.1 CMP Background 7
2.1.2 CMP Operations and Tool Configurations 7
2.1.3 CMP Performance Evaluation 8
2.1.3.1 Material Removal Rate and Non-uniformity 9
2.1.3.2 Planarization Capability 10
2.1.4 CMP Applications in Microelectronics 11
2.1.4.1 Front End of Line (FEOL) Applications 12
2.1.4.2 Middle of Line (MOL) Applications 14
2.1.4.3 BEOL End of Line (BEOL) Application 15
§ 2.2 Contact Formation and Its difficulties 16
§ 2.3 Corrosion 19
2.3.1 Corrosion Reaction 19
2.3.2 Corrosion Potentials and Currents 19
2.3.3 Galvanic corrosion 21
§ 2.4 BEOL Overview 22
2.4.1 BEOL introduction 22
2.4.2 RC Delay 24
2.4.3 Low-k dielectric materials 25
2.4.4 Cu interconnect integration scheme 28
§ 2.5 Reliabilities of Cu Interconnects 30
2.5.1 Electromigration 31
2.5.2 Stress Migration 33
2.5.3 Time Dependent Dielectric Breakdown (TDDB) 33
2.5.4 Reliability Statistics 36
2.5.5 Acceleration Models 37
§ 2.6 Summary 39
§ References 56

Chapter 3 Experimental Procedures and Techniques
§ 3.1 Wafer preparations 62
3.1.1 Contact loop wafers 62
3.1.2 BEOL loop wafers 63
§ 3.2 CMP process tools 63
3.2.1 WCMP 63
3.2.2 Cu CMP 64
§ 3.3 Analytic Techniques 64
3.3.1 Electrochemical Measurements 64
3.3.2 Atomic Force Microscopy (AFM) 65
3.3.3 Scanning Electron Microscope (SEM) 67
3.3.4 Transmission Electron Microscopy (TEM) 67
3.3.5 Secondary-Ion Mass Spectrometry (SIMS) and Time of Flight Secondary-Ion Mass Spectrometry (TOF-SIMS) 68
3.3.6 Angle-resolved X-ray Photoelectron Spectroscopy (AR-XPS) 69
3.3.7 Optical Beam Induced Resistance Change (OBIRCH) 71
§ 3.4 Electrical Measurements 71
3.4.1 EM lifetime test 71
3.4.2 TDDB lifetime test 72
§ References 80

Chapter 4 Electrochemical Studies of W Corrosion for Low Resistive Contact in the 28 nm Technology Node
§ 4.1 Background and Motivations 82
§ 4.2 Wafer Preparations 84
§ 4.3 W Nucleation Layer Depositions and WCMP Process 84
§ 4.4 Analytical Methods 85
§ 4.5 Results and Discussions 85
§ 4.6 Conclusions 88
§ References 98

Chapter 5 Defect Studies of Manufacturing Feasible Porous Low-k Dielectrics Direct Polish in 45nm Technology and beyond
§ 5.1 Background and Motivations 99
§ 5.2 Wafer Preparations 99
§ 5.3 Analytical Methods 100
§ 5.4 Results and Discussions 100
§ 5.5 Conclusions 103
§ References 113

Chapter 6 TDDB and EM Studies of the Effects of Post-CMP Cleaning for L40 Direct-Polishing Porous Low K Cu Interconnects
§ 6.1 Background and Motivations 114
§ 6.2 Wafer Preparations 117
§ 6.3 Analytical Methods 118
§ 6.4 Results and Discussions 119
6.4.1 The influence of Cu surface roughness on TDDB 119
6.4.2 The influence of Cu surface roughness on EM 121
§ 6.5 Conclusions 123
§ References 134

Chapter 7 The TDDB Failure Modes and Their Engineering Studies for Porous Low-K Dielectric Direct Polish Scheme
§ 7.1 Background and Motivations 139
§ 7.2 Wafer Preparations 140
§ 7.3 Analytical Methods 140
§ 7.4 Results and Discussions 140
7.4.1 Top Interface Failure 141
7.4.2 Sidewall Failure 142
7.4.3 Bottom Corner Failure 143
§ 7.5 Conclusions 144
§ References 152

Chapter 8 Conclusions and Prospects
§ 8.1 Conclusions 153
§ 8.2 Prospects 155

Appendix A: Author’s related publication List 157
Appendix B: Author’s Vita 163

參考文獻 Chapter 1
1. J.G. Ryan, R.M. Geffken, N.R. Poulin and J.R. Paraszczak, “The evolution of interconnection technology at IBM,” IBM J. Res. Dev., vol. 39, pp. 371-381, 1995.
2. M. R. Oliver (Ed.), “Chemical Mechanical Planarization of Semiconductor Materials”, Springer-Verlag, Berlin, 2004.
3. C.H. Kim, I.C. Rho, S.-H. Kim, I.K. Han, H.S. Kang, S.W. Ryu, and H.-J. Kim, “Pulsed CVD-W Nucleation Layer Using WF6 and B2H6 for Low Resistivity W,” J. Electrochem. Soc., vol. 156, pp. H685-H689, 2009.
4. T. Luoh, C.T. Su, T.H.Yang, K.C. Chen, C.-Y. Lu, “Advanced tungsten plug process for beyond nanometer technology,” Microelectronic Eng., vol. 85, pp. 1739-1747, 2008.

Chapter 2
1. J. M. Steigerwald, S.P. Murarka, and R.J. Gutmann, "Chemical Mechanical Planarization of Microelectronic Materials," John Wiley & Sons, New York, NY., 1997.
2. F. W. Preston, “The theory and design of plate glass polishing machines,” J. Soc. Glass Technol., vol. 11, pp. 214–256, Dec. 1927.
3. N.J. Brown, P.C. Baker, and R.T. Maney, "Optical Polishing of Metals,” Proc. SPIE, vol. 306, pp. 42-57, 1981.
4. S. Pandija, D. Roy, and S.V. Babu, "Achievement of high planarization efficiency in CMP of copper at a reduced down pressure," Microelectron. Eng., vol. 86, pp 367–373, 2009.
5. M. Krishnan, J. W. Nalaskowski, and L. M. Cook, “Chemical Mechanical Planarization: Slurry Chemistry, Materials, and Mechanisms,” Chem. Rev., vol. 110, PP. 178–204, 2010.
6. R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros, and M. Metz, " High-k/Metal-Gate Stack and Its MOSFET Characteristics," IEEE Electron Device Lett., vol. 25, pp. 408-410, 2004.
7. Y. Li, Ed: “Microelectronic Applications of Chemical Mechanical Planarization,” Wiley-Interscience: Hoboken, NJ, 2008.
8. U. Paik and J. G. Park, Ed: “Nanoparticles Engineering for Chemical-Mechanical Planarization: Fabrication of Next-Generation Nanodevices,” Taylor-Francis Group, LLC, pp. 9-25, 2010.
9. C.H. Kim, I.C. Rho, S.-H. Kim, I.K. Han, H.S. Kang, S.W. Ryu, and H.-J. Kim, "Pulsed CVD-W Nucleation Layer Using WF6 and B2H6 for Low Resistivity W", J. Electrochem. Soc., vol. 156, pp. H685-689, 2009.
10. T. Luoh, C.T. Su, T.H.Yang, K.C. Chen, C.-Y. Lu, "Advanced tungsten plug process for beyond nanometer technology," Microelectronic Eng., vol. 85, pp. 1739-1747, 2008.
11. A. Yutani , K. Ichinose, K. Maekawa, K. Asai, and M. Kojima, "Novel Contact-Plug Process with Low-Resistance Nucleation Layer Using Diborane-Reduction Tungsten Atomic-Layer-Deposition Method for 32nm Complementary Metal–Oxide–Semiconductor Devices and Beyond," Jap. J. Appl. Phys., vol. 47, pp. 2464–2467, 2009
12. T. Hinomura, A. Nishimura, M. Joei, H. Ohnaka, H. Miyajima, T. Kishida, "Low Resistance W-Contact for 32-nm Node Devices and Beyond," in Proc. IEEE Int. Interconnect Technol. Conf., 1, 2010. (art. no. 5510695)
13. S.H. Kim, N. Kwak, J. Kim, and H. Sohnb, "A Comparative Study of the Atomic-Layer-Deposited Tungsten Thin Films as Nucleation Layers for W-Plug Deposition," J. Electrochem. Soc., vol. 153, pp. G887-893, 2006.
14. S.H. Kim, E.S. Hwang, B.M. Kim, J.W. Lee, H.J. Sun, T. E. Hong, J.K. Kim, H. Sohn, J. Kim, and T.S. Yoon, "Effects of B2H6 Pretreatment on ALD of W Film Using a Sequential Supply of WF6 and SiH4," Electrochem. Solid-State Lett., vol. 8, pp. C155-C159, 2005.
15. C.C. Hung, Y.L. Wang, W.H. Lee and S.C. Chang, "Investigation of Static Corrosion Between W Metals and TiNx Barriers in a W Chemical-Mechanical-Polishing Slurry," J. Electrochem. Soc., vol. 155, pp. H469-H473, 2008.
16. A. E. Kaloyeros and E. Eisenbraun, "Untrafhin Diffusion Barriers/ Liners for Gigascale Copper Metallization," Annu. Rev. Mater. Sci., vol. 30, pp. 363-385, 2000.
17. S.H. Kim, J.K. Kim, N. Kwak, H. Sohn, J.W. Kim, S.H. Jung, M.R. Hong, S. H. Lee, and J. Collins, “Atomic Layer Deposition of Low-Resistivity and High-Density Tungsten Nitride Thin Films Using B2H6, WF6, and NH3,” Electrochemical and Solid-State Letters, vol. 9, pp. C54-C57, 2006.
18. S. Demuynck, A. Nackaerts, G. Van den bosch, T. Chiarella, J. Ramos, Zs. Tőkei, J. Vaes, N. Heylen, G. P. Beyer, M. Van Hove, T. Mandrekar1, R. Schreutelkamp, "Impact of Cu contacts on front-end performance: a projection towards 22nm node," in Proc. IEEE Int. Interconnect Technology Conf., pp. 178-180, 2006.
19. Y.L. Jiang, Q. Xie, X.P. Qu, D.W. Zhang, D. Deduytsche, C. Detavernier, "TaN/Ta as an Effective Diffusion Barrier for Direct Contact of Copper and NiSi," Electrochemical and Solid-State Letters, vol. 15, pp. H9-H13, 2012.
20. M. Tullmin, P.R. Roberge, "Corrosion of Metallic Materials," IEEE Trans. Reliab., vol. 44, pp. 271-284, 1995.
21. D. A. Jones, "Principles and Prevention of Corrosion (2nd edition)," Prentice Hall, Upper Saddle River NJ, 1996.
22. P. Mohan, T. Jiang, and V. Desai, "Studies on Galvanic Corrosion Effect in CMP of Cu and Barrier Layer Materials," Presented at the 208th Electrochemical Society Meeting, 2005.
23. T. Edwards and M. Steer, Foundations of Interconnect and Microstrip Design, John Wiley, New York, 2000.
24. J. D. Meindl, "Theoretical, practical and analogical limits in ULSI," in Proc. IEEE Int. Electron Device. Meet., pp. 8–13, Dec. 1983.
25. D. Silvester and C. Hu, "Analytical modeling and characterization of deep-sub-micrometer interconnect", Proc. IEEE, vol. 89, pp. 634-664, 2001.
26. A. Gill and V. Patel, "Ultralow-k dielectrics prepared by plasma-enhanced chemical vapor deposition," Appl. Phys. Lett., vol. 79, pp. 803-805, 2001.
27. S.P. Murarka, M. Eizenbergh, and A.K. Sinha (eds.), "Interlayer dielectrics for semiconductor technologies," Elsevier/Academic press, Amsterdam, Boston, 2003.
28. P.S. Ho, W.W. Lee, and J. Leu, "Low dielectric constant materials for IC applications," Springer, New York, 2002.
29. M.T. Bohr and Y.A. El-Mansy, "Technology for advanced high performance microprocessors," IEEE Trans. Electron. Dev., vol. 45, pp. 620-625, 1998.
30. M. Morgan, E.T. Ryan, J. Zaho, C. Hu, and P.S. Ho, "Low dielectric constant materials for ULSI interconnects," Annu. Rev. Mater. Sci., vol. 30, pp. 645-680, 2000.
31. G.N. Taylor and T.M. Wolf, "Oxygen plasma removal of thin polymer films," Polym. Eng. Sci., vol. 20, pp. 1087-1092, 1980.
32. B. Kastenmeier, K. Pfeifer, and A. Knorr, "Effective-K," Semicond. Int., vol. 27, p. 87, July 2004.
33. H. Kitoh, M. Mroyama, M. Sasaki, M. Iwasawa, and H. Kimura, " Formation of SiOF Films by Plasma-Enhanced Chemical Vapor Deposition Using (C2H5O)3SiF, Jpn. J. Appl. Phys., vol. 35, pp. 1464-1467, 1996.
34. A. Gill and V. Patel, "Interaction of hydrogen plasma with extreme low-K SiCOH dielectrics," J. Electrochem. Soc., vol. 151, pp. F133-F134, 2004.
35. J. Noguchi, T. Oshima, T. Matsumoto, S. Uno, and K. Sato, "Multilevel Interconnect with Air-Gap Structure for Next-Generation Interconnections," IEEE Trans. Electron. Dev., vol. 56, pp. 2675-2682, Nov. 2009.
36. E. Edelstein, J. Heidenreich, R. Goldblatt, W. Cote, C. Uzoh, N. Lustig, P. Roper, T. McDevitt, W. Motsiff, A. Simon, J. Dukovic, R. Wachnik, H. Rathore, R. Schulz, L. Su, S. Luce, and J. Slattery, "Full copper wiring in a sub-0.25 um CMOS ULSI technology," Tech. Dig. in IEEE Int. Electron Device. Meet., p.773, 1997.
37. T. Gupta, “Copper Interconnect Technology", New York: Springer, 2009.
38. I. A. Blech and H. Sello, “The failure of thin aluminum current-carrying strips on oxidized silicon,” Physics of Failure in Electronics, ser. USAF-RADC Series, vol. 5, pp. 496–505, 1966.
39. J. R. Black, “Mass transport of aluminum by momentum exchange with conducting electrons,” in Proc. of Int. Reliab. in Phys. Symp., pp.148–159, 1967.
40. I. A. Blech and C. Herring, “Stress generation by electromigration,” Appl. Phys. Lett. vol. 29, pp. 131–133, 1976.
41. C. S. Hau-Riege, “An introduction to Cu electromigration,” Microelectron. Reliab., vol. 44, pp. 195–205, 2004.
42. C.K. Hu, L. Gignac, R. Rosenberg, "Electromigration of Cu/low dielectric constant interconnects," Microelec. Reliab., vol. 46, pp. 213-231, 2006.
43. Y.L. Cheng, B.L. Lin, S.Y. Lee, C.C. Chiu, and K. Wu, "Cu Interconnect Width Effect, Mechanism and Resolution on Down-Stream Stress Electromigration," in Proc. Int. Reliab. Phys. Symp., pp. 128-133, 2007.
44. A. V. Vairagar, S. G. Mhaisalkar, and A. Krishnamoorthy, "Effect of surface treatment on electromigration in sub-micron Cu damascene interconnects," Thin Solid Film, vol. 462, pp. 325-329, 2004.
45. W. Shao, S. G. Mhaisalkar, T. Sritharan, A. V. Vairagar, H. J. Engelmann, O. Aubel, E. Zschech, A. M. Gusak, and K. N. Tu, "direct evidence of Cu/cap/liner edge being the dominant electromigration path in dual damascene Cu interconnects," Appl. Phys. Lett., vol. 90, 052106, 2007.
46. M.W. Lane, E.G. Liniger, J.R. Lloyd, "Relationship between interfacial adhesion and electromigration in Cu metallization," J. Appl. Phys., vol. 93, pp. 1417-1421, 2003.
47. M. Tada, M. Abe, H. Ohtake, N. Furutake, T. Tonegawa, K. Motoyama, M.K. Itos, M. Ueki, T. Takeuchi, S. Saito, K. Fujii, M. Sekine, Y. Hayashi, M. Tohara, " A Metallurgical Prescription for Electromigration (EM) Reliability Improvement in Scaled-down, Cu Dual Damascene Interconnects," in Proc. IEEE Int. Interconnect Technology Conf., pp. 89-91, 2006.
48. E. T. Ryan, J. Martin, G. Bonilla, S. Molis, T. Spooner, J. Widodo, J.-H. Kim, E. Liniger, A. Grill, and C.-K. Hue, " Line Resistance and Electromigration Variations Induced by Hydrogen-Based Plasma Modifications to the Silicon Carbonitride/Copper Interface," J. Electrochem. Soc., vol 154, H604-H610, 2007.
49. C.-K. Hu, L. Gignac, E. Liniger, B. Herbst, D. L. Rath, S. T. Chen, S. Kaldor, A. Simon, and W.-T. Tseng, "Comparison of Cu electromigration lifetime in Cu interconnects coated with various caps," Appl. Phys. Lett. , vol. 83, pp. 869-871, 2003.
50. T. Saito, H. Ashihara, K. Ishikawa, M. Miyauchi, Y. Yamada, and H. Nakano, "A Reliability Study of Barrier-Metal-Clad Copper Interconnects with Self-Aligned Metallic Caps," IEEE Trans. Electr. Dev., vol. 51, pp. 2129-2135, 2004.
51. T. Sullivan, “Reliability considerations for copper metallization in ULSI circuits”, in Proc. of the fifth international workshop on stress induced phenomena in metallization, pp. 39-50, 1999.
52. E.T. Ogawa, J.W. McPherson, J.A. Rosal, K.J. Dickerson, T.C. Chiu, L.Y. Tsung, M.K. Jain, T.D. Borifield, J.C. Ondrusek, and W.R. McKee, in Proc. Int. Reliab. Phys. Symp., p. 312, 2002.
53. I.C. Chen, S. Holland, and C. Hu, “Electrical Breakdown in Thin Gate and Tunneling Oxides”, IEEE Trans. Electron. Dev., vol. 32, pp. 413-422, 1985
54. C. Y. Chang and S. M. Sze, “ULSI Technology,” McGraw-Hill, Singapore, pp. 679–684, 1996.
55. W. Zhang, X. Zeng , W. Liu, Y. K. Lim , J. F. Liu, and E. C. Chua,” Study of Electric Field–Based Lifetime Projection Method in IMD TDDB,” in Proc. Int. Reliab. Phys. Symp., pp.938-942, 2010.
56. G. G. Gischia, K. Croes, G. Groeseneken and Z. Tőkei, “Study of Leakage Mechanism and Trap Density in Porous Low-K Materials,” in Proc. Int. Reliab. Phys. Symp, pp. 549-555, 2010.
57. K. H. Cheng and A. Krishnamoorthy, "Effect of ramp rate on dielectric breakdown in CU-SiOC interconnect," Thin Solid Films, vol. 462, pp. 316-320, 2004.
58. K. Croes, P.J. Roussel, G. Groeseneken, "Theoretical Aspects of Reliability Statistics and Data Analysis," Int. Reliab. Phys. Symp Tutorial, 2010.
59. J.W. McPherson and H.C. Mogul, “Underlying physics of the thermochemical E model in describing low field time-dependent dielectric breakdown in SiO2 thin films, J. Appl. Phys., vol. 84, pp. 1513-1523, 1998.
60. G.S. Haase, E.T. Ogawa, and J.W. McPherson, “Reliability analysis method for low-k interconnect dielectrics breakdown in integrated circuits, J. Appl. Phys., vol. 98, 034503, 2005.
61. C. Hu, “Ultra-large-scale integration device scaling and reliability,” J. Vac. Sci. Technol. B, vol. 12, pp. 3237-3241, 2009.
62. C. Hu, and Q.Lu, “A unified gate oxide reliability model,” in Proc. Int. Reliab. Phys. Symp., pp. 47-51, 1999.
63. F. Chen, O. Bravo, K. Chanda, P. McLaughlin, T. Sullivan, J. Gill, J. Lloyd, R. Kontra, and J. Aitken, “A Comprehensive Study of Low-k SiCOH TDDB Phenomena and Its Reliability Lifetime Model Development”, in Proc. Int. Reliab. Phys. Symp., pp. 46-53, 2002.
64. G. S. Haase, "An Alternative Model for Interconnect Low-K Dielectric Lifetime Dependence on Voltage”, in Proc. Int. Reliab. Phys. Symp., pp. 556-565, 2008.
65. N. Suzumura, S. Yamamoto, D. Kodama, H. Miyazaki, M. Ogasawara, J. Komori and E. Murakami, “Electric-Field and Temperature Dependencies of TDDB Degradation In Cu/Low-K Damascene Structures”, in Proc. Int. Reliab. Phys. Symp., pp. 138-143, 2008.
66. “International Technology Roadmap for Semiconductors (ITRS)”, Semiconductor International Association, 2010.
67. Y. Shacham-Diamand, T. Osaka, M. Datta, and T. Ohba, "Advanced Nanoscale ULSI Interconnects: Fundamentals and Applications," Springer, New York, 2009.

Chapter 3
1. A. Grill, "Plasma enhanced chemical vapor deposited SiCOH dielectrics: from low-k to extreme low-k interconnect materials," J. Appl. Phys., vol. 93, pp. 1785-1790, 2003.
2. A. Grill, V. Patel, K. P. Rodbell, E. Huang, M. R. Baklanov, K. P. Mogilnikov, M. Toney and H.-C. Kim, "Porosity in plasma enhanced chemical vapor deposited SiCOH dielectrics: A comparative study," J. Appl. Phys., vol. 94, pp. 3427-3435, 2003
3. C.W. Kaanta, S.G. Bombardier, W.J. Cote, W.R. Hill, G. Kerszykowski, H.S. Landis, D.J. Poindexter, C.W. Pollard, G.H. Ross, J.G. Ryan, S. Wolff, and J.E. Cronin, Proc. IEEE VLSI Multilevel Interconnection Conf., pp. 144-152, 1991.
4. M. Hiroi, M. Tada, H. Ohtake, S. Saito, T. Onodera, N. Furutake, Y. Harada, and Y. Hayashi, " Dual Hard Mask Process for low-k Porous Organosilica Dielectric in Copper Dual Damascene Interconnect Fabrication," in Proc. IEEE Int. Interconnect Technology Conf., pp. 295-297, 2001.
5. David W. Mogk (Dec 2011), “Time-of-Flight Secondary Ion Mass Spectrometry (ToF-SIMS)”, Available: http://serc.carleton.edu/research_education/geochemsheets/techniques/ToFSIMS.html
6. W.A.M. Aarnink, A. Weishaupt and A. van Silfhout, “Angle-resolved X-ray photoelectron spectroscopy (ARXPS) and a modified Levenberg-Marquardt fit procedure: a new combination for modeling thin layers“, Applied Surface Science, vol. 45, pp. 37-48, 1990.
7. Nikawa, K; Tozaki, S, "Principles Novel OBIC Observation Method for Detecting Defects in Al Stripes Under Current Stressing", in Proc. of the 19th International Symposium for Testing and Failure Analysis, pp. 303–310, 1993.
8. Nanoscience Education (Dec 2011), Available: http://www.nanoscience.com/education/AFM.html
9. G. C. Schwartz and K. V. Srikrishnan, ”Handbook of semiconductor interconnection technology“, 2nd ed., CRC/Taylor& Francis, Boca Raton, FL, 2006.
10. K. Wetzig and C. M. Schneider, "Metal based thin films for electronics“, 2nd ed., Wiley-VCH, Weinheim, 2006.

Chapter 4
1. C.H. Kim, I.C. Rho, S.-H. Kim, I.K. Han, H.S. Kang, S.W. Ryu, and H.-J. Kim, "Pulsed CVD-W Nucleation Layer Using WF6 and B2H6 for Low Resistivity W", J. Electrochem. Soc., vol. 156, pp. H685-689, 2009.
2. T. Luoh, C.T. Su, T.H.Yang, K.C. Chen, C.-Y. Lu, "Advanced tungsten plug process for beyond nanometer technology," Microelectronic Eng., vol. 85, pp. 1739-1747, 2008.
3. A. Yutani , K. Ichinose, K. Maekawa, K. Asai, and M. Kojima, "Novel Contact-Plug Process with Low-Resistance Nucleation Layer Using Diborane-Reduction Tungsten Atomic-Layer-Deposition Method for 32nm Complementary Metal–Oxide–Semiconductor Devices and Beyond," Jap. J. Appl. Phys., vol. 47, pp. 2464–2467, 2009
4. T. Hinomura, A. Nishimura, M. Joei, H. Ohnaka, H. Miyajima, T. Kishida, "Low Resistance W-Contact for 32-nm Node Devices and Beyond," in Proc. IEEE Int. Interconnect Technology Conf., 1, 2010. (art. no. 5510695)
5. S. H. Kim, N. Kwak, J. Kim, and H. Sohnb, "A Comparative Study of the Atomic-Layer-Deposited Tungsten Thin Films as Nucleation Layers for W-Plug Deposition," J. Electrochem. Soc., vol. 153, pp. G887-893, 2006.
6. S. H. Kim, E. S. Hwang, B. M. Kim, J. W. Lee, H. J. Sun, T. E. Hong, J. K. Kim, H. Sohn, J. Kim, and T. S. Yoon, "Effects of B2H6 Pretreatment on ALD of W Film Using a Sequential Supply of WF6 and SiH4," Electrochem. Solid-State Lett., vol. 8, pp. C155-C159, 2005.
7. C. C. Hung, Y. L. Wang, W. H. Lee and S. C. Chang, "Investigation of Static Corrosion between W Metals and TiNx Barriers in a W Chemical-Mechanical-Polishing Slurry," J. Electrochem. Soc., vol. 155, pp. H469-H473, 2008.

Chapter 5
1. H. N. Tai, J. Y. Fang, C. L. Hsu, C. H. Chen, C. C. Huang, “Study on Post CMP Cleaning on Ultra Low-K Dielectric for Direct Barrier CMP Development in L45 IC Fabrication”, in Proc. 2007 CMP-MIC Conf., p.p. 129-132, 2007.
2. S. Kondo, B.U. Yoon, S.G. Lee, S. Tokitoh, K. Misawa, T. Yoshie, N. Ohashi and N. Kobayashi, "Damage-free CMP towards 32nm-node porous low-k (k=1.6)/Cu integration," Tech. Dig. in 2004 Symp. on VLSI Technol., pp. 68-69, June 2004.
3. S.G. Lee, T. Yoshie, Y. Sudo, E. Soda, K. Yoneda, B. U. Yoon, H. Kobayashi, S. Kageyama, K. Misawa, S. Kondo, T. Nasuno, Y. Matsubara, N. Ohashi and N. Kobayashi, "PECVD low-k SiOC (k=2.8) as a cap layer for 200nm pitch Cu interconnect using porous low-k dielectrics (k=2.3)", in Proc. IEEE Int. Interconnect Technology Conf., pp. 63-65, Jun 2004.
4. C. L. Hsu, W. C. Su, S. J. Chen, Y. D. Tsai, C. C. Huang. S. F. Tzou, Q. Ye, T. Thomas, R. Lavoie, H. Li, C. F. Dai, “Enhancing Copper Surface Roughness via CMP for Optimal Performance“, in proc. 2006 ECS Int. Semicond.r Technol. Conf., pp. 505-510, 2006.

Chapter 6:
1. E.T. Ogawa, J. Kim, G.S. Haase, H.C. Mogul, J.W. McPherson, "Leakage, Breakdown, and TDDB Characteristics of Porous Low-k Silica-Based Interconnect Dielectrics," in Proc. International Reliability in Physics Symp., pp. 166-172, 2003.
2. J. Noguchi, "Dominant Factors in TDDB Degradation of Cu Interconnects," IEEE Trans. Electr. Dev., vol. 52, pp. 1743-1750, 2005.
3. L. Arnaud, D. Galpin, S. Chhun, C. Monget, E. Richard, D. Roy, C. Besset, M. Vilmay, L. Doyen, P. Waltz, E. Petitprez, F. Terrier, G Imbert, and Y Le Friec,"Reliability Failure Modes in Interconnects for the 45nm Technology Node and Beyond," Proc. IEEE Int. Interconnect Technol. Conf., p. 179-181, 2009.
4. E. Soda, N. Oda, S. Ito, S. Kondo, S. Saito, and S. Samukawa, " Reduction effect of line edge roughness on time-dependent dielectric breakdown lifetime of Cu/low-k interconnects by using CF3I etching," J. Vac. Sci. Technol. B, vol. 27, pp. 649-653, 2009.
5. F. Chen and M. Shinosky, "Addressing Cu/Low-k Dielectric TDDB-Reliability Challenges for Advanced CMOS Technologies," IEEE Trans. Electr. Dev., vol. 56, pp. 2-12, 2009.
6. J. Gambino, F. Chen, and J. He, " Copper Interconnect Technology for the 32 nm Node and Beyond," in proc. of IEEE 2009 Custom Intergrated Circuits Conf., pp. 141-148, 2009.
7. S.C. Lee, A. S. Oates, and K.-M. Chang," Geometric Variability of Nanoscale Interconnects and Its Impact on the Time-Dependent Breakdown of Cu/Low-k Dielectrics," IEEE Trans.Dev. Mater. Re., vol. 10, pp. 307-316, 2010.
8. J. Noguchi, N. Ohashi, T. Jimbo, H. Yamaguchi, K. Takeda, and K. Hinode, " Effect of NH3-Plasma Treatment and CMP Modification on TDDB Improvement in Cu Metallization," IEEE Trans. Electr. Dev., vol. 48, 1340-1345, 2001.
9. J. Noguchi, N. Konishi, and Y. Yamada, " Influence of Post-CMP Cleaning on Cu Interconnects and TDDB Reliability," IEEE Trans. Electr. Dev., vol. 52, pp.934-941, 2005.
10. N. Konishi, Y. Yamada, J. Noguchi, T. Jimbo and O. lnoue, "Influence of CMP Process on Defects in SiOC Films and TDDB Reliability," in Proc. IEEE Int. Interconnect Technology Conf., pp. 123-125, 2005.
11. Y. Yamada, N. Konishi, J. Noguchi, and T. Jimbo, "Influence of CMP Slurries and Post-CMP Cleaning Solutions on Cu Interconnects and TDDB Reliability," J. Electrochem. Soc., vol. 155, pp. H485-H490, 2008.
12. F. Chen, O. Bravo, D. Harmon, M. Shinosky, J. Aitken, "Cu/low-k dielectric TDDB reliability issues for advanced CMOS technologies," Microelectron. Reliab., vol. 48, pp. 1375-1383, 2008.
13. W.C. Lin, Jack Lin, T.C. Tsai, C.M. Hsu, C.C. Liu, J.F. Lin, C.C. Hwang, J.Y. Wu, " Effects of Cu surface roughness on TDDB for direct polishing ultra-low k dielectric Cu interconnects at 40 nm technology node and beyond," in press in Microelectron. Eng., 2011.
14. C.K. Hu, L. Gignac, R. Rosenberg, "Electromigration of Cu/low dielectric constant interconnects," Microelec. Reliab., vol. 46, pp. 213-231, 2006.
15. Y.L. Cheng, B.L. Lin, S.Y. Lee, C.C. Chiu, and K. Wu, "Cu Interconnect Width Effect, Mechanism and Resolution on Down-Stream Stress Electromigration," Proc. Int.Reliab. in Phys. Symp., pp. 128-133, 2007.
16. A. V. Vairagar, S. G. Mhaisalkar, and A. Krishnamoorthy, "Effect of surface treatment on electromigration in sub-micron Cu damascene interconnects," Thin Solid Film, vol. 462, pp. 325-329, 2004.
17. W. Shao, S. G. Mhaisalkar, T. Sritharan, A. V. Vairagar, H. J. Engelmann, O. Aubel, E. Zschech, A. M. Gusak, and K. N. Tu, "direct evidence of Cu/cap/liner edge being the dominant electromigration path in dual damascene Cu interconnects," Appl. Phys. Lett., vol. 90, 052106, 2007.
18. K. Abe and H. Onoda," Effects of Ti insertion between Cu and TiN layers on reliability in Cu/Ti/TiN/Ti layered damascene interconnects," J. Vac. Sci. Technol. B, vol. 21, pp. 1161-1168, 2003.
19. P. C. Wang and R. G. Filippi, " Electromigration threshold in copper interconnects," Appl. Phys. Lett., vol. 78, 3598-3600, 2001.
20. R. Gonella, J. Torres, P. Motte, E. V. D. Vegt, and J. M. Gilet, "Impact of process steps on electrical and electromigration performances of copper interconnects in damascene architecture," Microelectronic Reliability, vol. 40, pp. 1329-1334 ,2000.
21. M.W. Lane, E.G. Liniger, J.R. Lloyd, "Relationship between interfacial adhesion and electromigration in Cu metallization," J. Appl. Phys., vol. 93, pp. 1417-1421, 2003.
22. J. R. Lloyd, M. W. Lane, E. G. Liniger, C.-K. Hu, T. M. Shaw, and R. Rosenberg, "Electromigration and Adhesion," IEEE Trans. Dev. Mater. Re., vol. 5, pp. 113-118, 2005.
23. M. Tada, M. Abe, H. Ohtake, N. Furutake, T. Tonegawa, K. Motoyama, M.K. Itos, M. Ueki, T. Takeuchi, S. Saito, K. Fujii, M. Sekine, Y. Hayashi, M. Tohara, " A Metallurgical Prescription for Electromigration (EM) Reliability Improvement in Scaled-down, Cu Dual Damascene Interconnects," in Proc. IEEE Int. Interconnect Technology Conf., pp. 89-91, 2006.
24. S. Yokogawa, H. Tsuchiya, "Effects of Al doping on the electromigration performance of damascene Cu interconnects," J. Appl. Phys., vol. 101, 013513, 2007.
25. E. T. Ryan, J. Martin, G. Bonilla, S. Molis, T. Spooner, J. Widodo, J.-H. Kim, E. Liniger, A. Grill, and C.-K. Hue, " Line Resistance and Electromigration Variations Induced by Hydrogen-Based Plasma Modifications to the Silicon Carbonitride/Copper Interface," J. Electrochem. Soc., vol 154, H604-H610, 2007.
26. C.-K. Hu, L. Gignac, E. Liniger, B. Herbst, D. L. Rath, S. T. Chen, S. Kaldor, A. Simon, and W.-T. Tseng, "Comparison of Cu electromigration lifetime in Cu interconnects coated with various caps," Appl. Phys. Lett. , vol. 83, pp. 869-871, 2003.
27. T. Saito, H. Ashihara, K. Ishikawa, M. Miyauchi, Y. Yamada, and H. Nakano, "A Reliability Study of Barrier-Metal-Clad Copper Interconnects with Self-Aligned Metallic Caps," IEEE Trans. Electr. Dev., vol. 51, pp. 2129-2135, 2004.
28. J. Noguchi, T. Oshima, N. Konishi, K. Ishikawa, K. Sato, S. Uno, S. Hotta, T. Saito, and H. Aoki, " Integration and Reliability of Cu–SiOC Interconnect for ArF/90-nm Node CMOS Technology," IEEE Trans. Electr. Dev., vol. 51, pp. 2168-2174, 2004
29. A. Grill, "Plasma enhanced chemical vapor deposited SiCOH dielectrics: from low-k to extreme low-k interconnect materials," J. Appl. Phys., vol. 93, pp. 1785-1790, 2003.
30. A. Grill, V. Patel, K. P. Rodbell, E. Huang, M. R. Baklanov, K. P. Mogilnikov, M. Toney and H.-C. Kim, "Porosity in plasma enhanced chemical vapor deposited SiCOH dielectrics: A comparative study," J. Appl. Phys., vol. 94, pp. 3427-3435, 2003
31. C.W. Kaanta, S.G. Bombardier, W.J. Cote, W.R. Hill, G. Kerszykowski, H.S. Landis, D.J. Poindexter, C.W. Pollard, G.H. Ross, J.G. Ryan, S. Wolff, and J.E. Cronin, Proc. IEEE VLSI Multilevel Interconnection Conf., pp. 144-152, 1991
32. M. Hiroi, M. Tada, H. Ohtake, S. Saito, T. Onodera, N. Furutake, Y. Harada, and Y. Hayashi, " Dual Hard Mask Process for low-k Porous Organosilica Dielectric in Copper Dual Damascene Interconnect Fabrication," in Proc. IEEE Int. Interconnect Technology Conf., pp. 295-297, 2001.
33. M. H. Lin, Y. L. Lin, J. M. Chen, M.-S. Yeh, K. P. Chang, K. C. Su, and Tahui Wang, "Electromigration Lifetime Improvement of Copper Interconnect by Cap/Dielectric Interface Treatment and Geometrical Design," IEEE Trans. Electr. Dev., vol. 52, pp. 2602-2608, 2005.
34. L. Dumas, S. Verrier, A. Achen, J. Hetzner, M. Proust, C. Rossato, C. Richard, P. Caubet, T. Jagueneau, C. Fellous, E. Serret, J.-C. Giraudin, " Electromigration and adhesion improvements of Thick Cu/BCB architecture in BiCMOS RF technology," in Proc. of the 5th WSEAS Int. Conf. on Microelectronics, Nanoelectronics, Optoelectronics, pp. 138-141, 2006.

Chapter 7
1. J. Kim, E. T. Ogawa and J. W. McPherson, “Time Dependent Dielectric Breakdown Characteristics of Low-k Dielectric (SiOC) Over a Wide Range of Test Areas and Electric Fields” in Proc. 2007 Int. Reliab. Phys. Symp., pp. 399-404, 2007.
2. F. Chen, J. R. Lloyd, K. Chanda, R. Achanta, O. Bravo, A. Strong, P. S. McLaughlin, M. Shinosky, S. Sankaran, E. Gebreselasie, “Line Edge Roughness and Spacing Effect on Low-k TDDB Characteristics,” in Proc. 2008 Int. Reliab. Phys. Symp., pp. 132-137, 2008.
3. G. S. Haase, “An Alternative Model For Interconnect Low-K Dielectric Lifetime Dependence on Voltage” in Proc. 2008 Int. Reliab. Phys. Symp., pp. 556-565, 2008.
4. C. L. Hsu, J. Y. Fang, A. Yu, J. Lin, C. Huang, J. Y. Wu, and D. C. Perng, “Defect Study of Manufacturing Feasible Porous Low k Dielectrics Direct Polish for 45nm Technology and beyond,” in Proc. 2009 IEEE Int. Interconnect Technol. Conf., pp. 140-142, 2009.
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