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系統識別號 U0026-1508201317215800
論文名稱(中文) 使用Linux作業系統驗證之十三階管線化軟體層級處理器
論文名稱(英文) A 13-stage Pipeline Soft Processor Core Verified by Linux OS
校院名稱 成功大學
系所名稱(中) 電腦與通信工程研究所
系所名稱(英) Institute of Computer & Communication
學年度 101
學期 2
出版年 102
研究生(中文) 陳胤孜
研究生(英文) Yin-Tz Chen
學號 Q36994184
學位類別 碩士
語文別 中文
論文頁數 67頁
口試委員 指導教授-陳中和
口試委員-張雲南
口試委員-賴柏承
口試委員-邱瀝毅
口試委員-張大緯
中文關鍵字 計算機架構  管線化處理器  暫存器轉移層級處理器  作業系統開機 
英文關鍵字 computer architecture  register transfer level pipeline processor  register transfer level processor  operating system porting 
學科別分類
中文摘要 本論文主要以ARM指令級架構建構一暫存器轉移層級(RTL)之高速處理器。在RTL層級設計中,以十三級管線化的架構實現高速處理器,並附加上危障前饋處理以及跳躍預測。為了要驗證處理器的完整性以及正確性,執行程式便是一最佳手段。但由於程式特性的緣故,一般程式僅能驗證到處理器的基本功能,許多進階的功能則無法被印證。作業系統特性不僅能驗證基本的功能,而且也能包含驗證進階功能的部分,而達到完整的功能驗證。

本論文採用實驗室先前以SystemC完成的Multi-core Virtual Platform作為實驗之驗證平台,並借由Modesim提供協同模擬環境,達成全系統階級模擬驗證。以Linux kernel 2.6.38.7做為開機使用的作業系統,合成過後的處理器可以達到333MHz的執行速度。在執行效能方面,以完美的快取模型以及加入跳躍預測機值及資料危障處理,IPC最佳表現有高達0.2844。
英文摘要 This thesis is mainly about building a high-speed processor with register transfer level (RTL) under ARM instruction set architecture. In terms of register-transfer level design, this processor is implemented with a 13-stage pipeline architecture along with a forwarding unit and a branch predictor. The best way to verify the integrality and correctness of the processor is through running programs. However, due to the characteristics of normal programs, they can verify only the basic functions of the processor, and leaving many advanced functions unverified. The characteristics of general operating systems will not only verify the basic functions but also the advanced functions of the processor, and therefore achieves full-function verification.

This thesis adopts Multi-core Virtual Platform which is finished with SystemC level for full-system simulation and verification in Modelsim Co-Sim environment. This platform takes Linux kernel 2.6.38.7 for operating system and achieves about 333MHz executing rate in post-synthesis simulation. By adding branch predictor and forwarding unit into CPU architecture with perfect cache model, the performance of IPC reaches up to 0.2844.
論文目次 摘要 1
Abstract 2
誌謝 3
目錄 4
表目錄 6
圖目錄 7
Chapter 1 序論 9
1-1 研究動機 9
1-2 內容編排 9
Chapter 2 處理器介紹 10
2-1 ARM指令級架構(ISA)介紹 10
2-1-1 執行模式(Execution Mode) 11
2-1-2 暫存器檔案(Register File) 12
2-1-3 指令類型 15
2-1-4 例外處理(Exception Handling) 16
2-2 ARM 處理器核心(CPU core)介紹 17
2-2-1 支援延伸(Supported Extensions) 18
2-2-2 管線架構(Pipeline Architecture) 22
2-3 ARM 相關處理器介紹 24
2-3-1 StrongARM 24
2-3-2 XScale 24
2-3-3 Faraday 24
Chapter 3 CasA8 core架構 25
3-1 CPU架構 25
3-1-1 Fetch級 28
3-1-2 Decode級 30
3-1-3 Execute級 37
3-2 精確中斷(precise interrupt)機制 42
3-3 跳躍預測(Branch Prediction)機制 44
3-4 危障偵測(Hazard Detection) 46
3-5 前饋機制(Forwarding) 48
Chapter 4 驗證環境與結果 50
4-1 作業系統開機成果 50
4-1-1 系統環境 50
4-1-2 合成結果 52
4-1-3 作業系統開機結果 54
4-1-4 作業系統開機成果比較 56
4-2 效能評估 57
4-2-1 危障偵測&前饋機制效能評估 57
4-2-2 跳躍預測機制之效能評估 62
Chapter 5 總結 64
5-1 結論 64
5-2 未來展望 65
參考文獻 66
參考文獻 [1] Synopsys, Inc., “SystemC, Version 2.0,”
http://www.systemc.org.

[2] ARM Corporation, "ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition," 2008

[3] ARM Corporation, "ARM7TDMI Technical Reference Manual," 2004

[4] ARM Corporation, "ARM1156T2F-S™ Technical Reference Manual," 2007

[5] ARM Corporation, "Cortex™-A8 Technical Reference Manual, Revision: r3p2," 2009

[6] Steve Furber, “ARM system-on-chip architecture, 2nd edition," Addison Vesley, 2000

[7] Chien-Te Liu, "CASL Hypervisor and its Virtualization Platform," 2012 master thesis of National Cheng Kung University, Tainan, Taiwan, July, 2012

[8] Hsun-Wei Kao, " Embedded Processor Verification using Particular Characteristics of Linux Operating System," 2006 master thesis of National Cheng Kung University, Tainan, Taiwan, July, 2006

[9] Chen-Chien Wang, "Design and Implementation of a Dual-ISA Embedded Microprocessor," 2005 master thesis of National Cheng Kung University, Tainan, Taiwan, July, 2005

[10] Montanaro, James et al., "A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor," Digital Technical Journal, vol. 9, no. 1. pp. 49–62., 1997

[11] PR Newswire, "Digital targets supercharged StrongARM chip at consumer electronics market," 5 February, 1996.
http://www.thefreelibrary.com/DIGITAL+TARGETS+SUPERCHARGED+StrongARM+CHIP+AT+CONSUMER+ELECTRONICS...-a017919435

[12] Intel, Inc., "3rd Generation Intel XScale(R) Microarchitecture Developer's Manual," May, 2007
http://www.intel.com/design/intelxscale/316283.htm

[13] Intel, Inc., "Intel System-On-A-Chip Media Processor Powers New Generation Of Consumer Electronics Devices," 17 April, 2007
http://www.intel.com/pressroom/archive/releases/2007/20070416comp_a.htm

[14] Keil, "Device Database,"
http://www.keil.com/dd/parms/arm.htm

[15] Faraday Technology, "Processor Core,"
http://www.faraday-tech.com/html/Product/IPProduct/ProcessorCores/index.htm

[16] ARM Corporation, "ARM Extends Cortex Family with First Processor Optimized for FPGA", 19 March, 2007.
http://www.arm.com/zh/about/newsroom/17017.php

[17] "Arm strengthens Java compilers: New 16-Bit Thumb-2EE Instructions Conserve System Memory" by Tom R. Halfhill, 11 July, 2005.
http://www.linleygroup.com/newsletters/newsletter_detail.php?num=4348

[18] ARM Corporation, "ARM, Gemalto and Giesecke & Devrient Form Joint Venture To Deliver Next-Generation Security For Services Running On Connected Devices," 03 April, 2012.
http://www.arm.com/zh/about/newsroom/arm-gemalto-giesecke-devrient-form-joint-venture-deliver-next-generation-security.php

[19] Wookey & Tak-Shing,“Porting the Linux Kernel to a new ARM Platform,”White Paper, Aleph One, 2002
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