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系統識別號 U0026-1502201715421400
論文名稱(中文) 能考量時序用來實現低功耗設計之實體設計方法論
論文名稱(英文) Timing-Aware Physical Design Methodologies for Implementing Low Power Designs
校院名稱 成功大學
系所名稱(中) 電機工程學系
系所名稱(英) Department of Electrical Engineering
學年度 105
學期 1
出版年 106
研究生(中文) 許雅婷
研究生(英文) Ya-Ting Shyu
學號 N28971285
學位類別 博士
語文別 英文
論文頁數 102頁
口試委員 召集委員-吳文慶
口試委員-劉濱達
口試委員-楊清淵
口試委員-蔡建泓
口試委員-魏嘉玲
口試委員-丁信文
指導教授-張順志
共同指導教授-林家民
中文關鍵字 時脈緩衝器功耗降低  正反器合併  多位元正反器  低功耗設計  突波電流  混合繞線架構  電源閘控 
英文關鍵字 Clock power reduction  flip-flop merging  hybrid routing structure  low-lower design  multi-bit flip-flop  power gating  rush current 
學科別分類
中文摘要 隨著製程進步,單一嵌入式設計中能夠包含越來越多的元件,這使得晶片中的功耗密度大幅提升。然而,隨著可攜式電子裝置的普及,如何能夠降低功率消耗已經成為VLSI 設計最重要的議題。降低功率消耗不僅能延長電池使用壽命,還能夠避免因為晶片過熱而影響導致其效能降低。
目前已經存在許多用來降低系統功率消耗的設計技術,其中多位元正反器應用技術及電源閘控技術是其中最有效的方法。然而,雖然這些方法可以有效的降低設計的功率消耗,它卻會大幅提升實體設計的複雜度。舉例來說,在實體設計流程中使用一個多位元正反器取代原始電路多個正反器,如果選取的正反器不適當或是擺置位置不佳,即可能會影響原本設計之時序,導致其效能降低,甚至影響晶片功能之正確性。而在電路中應用電源閘控技術時,若無法在實體設計時適當控制電源閘開關打開之時間,則可能會引起過大湧浪電流而造成系統穩定度降低,或是使得整體電路之反應時間大幅增加。
因此,在這份論文中分別針對多位元正反器應用技術及電源閘控技術提出一個實體設計流程,我們針對這兩項技術在實體設計所可能導致之問題,分別提出相對應之解決方法,使得此兩項技術得以應用到系統設計,不會因為時序問題而對系統造成效能或功能性的破壞。實驗結果顯示我們提出的方法是可行且有效率的。在多位元正反器技術應用方面,所提出的演算法可以在不破壞時序限制的情況下降低功率消耗,並同時最小化繞線長度。而在電源閘控技術應用方面,提出的方法可以使系統避免因過大的湧浪電流而造成的損壞,並更進一步提升系統穩定度。
英文摘要 Due to the prevalence of portable electronic products, lower power attracts more attention for circuit designs. However, as technology advances, an SOC design can contain more and more components, which lead to a higher power density. Hence, lower power becomes one of the most important issues in modern VLSI designs. Reducing power consumption not only can enhance battery life but also can avoid performance degradation induced by the overheating problem.
There have been many lower power design techniques proposed to reduce system power consumption. Among these techniques, the multi-bit flip-flop and the power-gated
are considered as the most effective approaches. Although these two methods both can reduce power consumption, they also increase implementation complexity of the physical
design. For instance, we have to replace several single-bit flip-flops by a single multi-bit flip-flop when the multi-bit flip-flop technique is applied to a design. But the timing in an original layout may be affected if an improper set of single-bit flip-flops is selected or a new inserted multi-bit flip-flop is placed at improper location. This will result in performance degradation or even failure in the functionality. Besides, when a power-gated technique is applied to a design, it may cause severe rush current if the turned-on sequence of power
switches or their timing are not properly controlled, and thus the reliability of a system is degraded and the response time is increased.
This dissertation presents two design methodologies which respectively target on implementing multi-bit flip-flops and power-gated techniques in the physical design. Since both of two techniques may induce timing-related issues, our approaches show the methodologies to resolve these problems and make them feasible in real VLSI designs. The experimental results have demonstrated the efficiency and effectiveness of our approaches. For the multi-bit flip-flop technique, our algorithm can achieve power reduction and simultaneously minimize wirelength without violating timing constraint. For the power gated technique, the proposed methodology can avoid occurrence of large rush current; hence, the reliability of a design is maintained.
論文目次 Abstract (Chinese) I
Abstract III
Table of Contents VII
List of Tables X
List of Figures XI
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Overview of the Dissertation 2
1.2.1. Approach of Power Reduction by Using Multi-Bit Flip-Flops 2
1.2.2. Methodology to Control Turn-On Sequence of Power Switches for Power Gating Designs 3
1.3 Thesis Organization 3
Chapter 2 Background Knowledge 5
2.1 Power consumption in circuit design 5
2.1.1. Dynamic Power 5
2.1.2. Static Power 8
2.2 Low Power Techniques 9
2.2.1. Gate Level Power Optimization 9
2.2.2. Multi-threshold Logics 10
2.2.3. Clock Network Power Saving 10
2.2.4. Power Network Management 12
2.3 Usage of Multi-Bit Flip-Flops in Clock Network 14
2.3.1. Structure 14
2.3.2. Design Concerns 15
2.3.3. Related Work 16
2.4 Power-Gated Design 19
2.4.1. Structure 19
2.4.2. Design Concerns of Rush Current and Wake-Up Time 21
2.4.3. Related Work 22
Chapter 3 Approach of Power Reduction by Using Multi-Bit Flip-Flops 24
3.1 Problem Formulation 24
3.2 Algorithm 26
3.2.1. Placement Space Determination 27
3.2.2. Combination Table Construction 30
3.2.3. Flip-Flop Merging 36
3.3 Computation Complexity Analysis 42
3.4 Experiment Results 43
3.4.1. Performance Comparison with Chang et al. [26] 43
3.4.2. Average-Case Performance 47
3.5 Summary 49
Chapter 4 Methodology to Control Turn-on Sequence of Power Switches for Power Gating Designs 51
4.1 Methodology for Power Switches Turn-on Sequence Determination 51
4.2 Power Network Modeling 54
4.2.1. C1C2 Model with Leakage Resistance 54
4.2.2. Equations for Estimating Voltage 57
4.2.3. Equations for Estimating Rush Current 60
4.3 Algorithm 61
4.3.1. Overview of Algorithm Flow 62
4.3.2. Power Switches Selection 63
4.3.3. Determination of the Depth of Daisy-Chain 64
4.3.4. Construction of Daisy-Chain 68
4.3.5. Construction of Distributed Fishbone 70
4.4 Experiment Results 71
4.4.1. Waveform Comparison with HSPICE Simulation Results 71
4.4.2. Quality of Solutions Generated by ILP Formulation 76
4.4.3. Test Cases Simulation Results 77
4.5 Summary 79
Chapter 5 Conclusions and Future Work 81
5.1 Conclusions 81
5.2 Future Work 82
5.2.1. More Precise Power Network Equivalent Model Formulation 82
5.2.2. Better Routing Structure Exploring 83
5.2.3. Robustness-aware Routing Structure Construction 84
5.2.4. Power Verification Methodology for Low Power Technique Implementation at Early Design Stage 86
Appendix-1 87
References 92
Publication List 100
A. Transaction / Journal Papers 100
B. Conference Papers 101
C. Awards 102
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