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系統識別號 U0026-1408201815394800
論文名稱(中文) 多閘極金氧半場效電晶體之次臨界行為研究及其次臨界邏輯電路之應用
論文名稱(英文) The Investigation on Subthreshold Behavior Model for the Multiple-Gate MOSFETs and Its Application of Subthreshold Logic Gate
校院名稱 成功大學
系所名稱(中) 微電子工程研究所
系所名稱(英) Institute of Microelectronics
學年度 106
學期 2
出版年 107
研究生(中文) 高鴻文
研究生(英文) Hong-Wun Gao
學號 Q18031051
學位類別 博士
語文別 英文
論文頁數 186頁
口試委員 指導教授-王永和
共同指導教授-江德光
口試委員-洪茂峰
口試委員-黃建榮
召集委員-莊紹勳
口試委員-荊鳳德
口試委員-張廖貴術
口試委員-陳英忠
口試委員-林吉聰
中文關鍵字 多閘極金氧半場效電晶體  短通道行為  超低功率消耗  直流行為模型  次臨界邏輯閘 
英文關鍵字 Multiple-Gate MOSFETs  Short-Channel Effect  Ultra Low Power  DC Behavior Model  Subthreshold Logic Gate 
學科別分類
中文摘要 隨著科技的進步以及行動設備、無線網路和其他低功耗設備的發展,功率消耗已經成為電路設計中重要的議題。最近,由於超大積體電路之漏電流、溫度控制及可靠性問題的增加,超低功耗電路很快地引起廣大的關注。根據研究,供應電壓低於元件臨界電壓的次臨界操作可以顯著地降低電路能源的消耗。於此同時,由於閘極方向長度的縮短,通道上的閘極控制效率降低,傳統平面電晶體(Planar Transistor)面臨越來越嚴峻的挑戰,漏電流及短通道效應(SCEs)的影響變得越來越嚴重。為了解決上述所提到的問題,絕緣層上覆矽(SOI)技術中的多閘極元件結構如:雙閘極金氧半場效電晶體(Double-Gate MOSFET)、三閘極金氧半場效電晶體(Triple-Gate MOSFET or FinFET)、環繞式閘極金氧半場效電晶體(Gate-All-Around MOSFET)被提出能有效抑制短通道效應的影響及延續超低功率閘極金氧半場效電晶體(ULP MOSFETs)微縮到奈米級的尺寸。目前為止,儘管有文獻對靜態互補式金氧半場效電晶體次臨界邏輯電路之類比/交流行為(Analog/AC Behavior)進行了廣泛的分析,但是對直流行為(DC Behavior)分析的文獻卻非常少,特別是針對邏輯擺幅(Logic Swing)、雜訊邊界(Noise Margin)和平均消耗功率(Average DC Power Consumption)的分析,除此之外,上述所提到的文獻僅針對傳統平面金氧半場效電晶體的次臨界邏輯行為進行研究分析,不適用於多閘極金氧半場效電晶體。因此,本文針對多閘極金氧半場效電晶體上次臨界行為特性進行探討,並將多閘極金氧半場效電晶體套用在邏輯電路上,去探討其邏輯電路的特性變化。
本論文基於多閘極金氧半電晶體之次臨界行為解析模型(Subthreshold Behavior Model),推導出了次臨界邏輯閘(Subthreshold Logic Circuit)直流行為解析模型(DC Behavior Model),包含邏輯擺幅(Logic Swing)、雜訊邊界(Noise Margin)和平均消耗功率(Average DC Power Consumption),並且對次臨界邏輯電路的直流特性進行深入的分析。由於它可適用於任何邏輯類型,因此採用反向器作為參考電路。本文中,率先介紹簡單且精確的多閘極金氧半電晶體之次臨界行為模型(Subthreshold Behavior Model),接著,將詳細探討超低電壓操作下的DC直流行為(DC Behavior)。通過超低電壓操作可以實現極低的功耗,而低功耗的代價則是降低的速度和動態範圍。 然而,次臨界邏輯電路主要用於電路設計中超低功耗端的應用。因此,次臨界邏輯電路適合於特定應用(例如新興的穿戴式設備、IC卡、無線傳感器和其他電池供電的應用,如物聯網),這些應用不需要非常高的性能。
我們使用混合模式元件/電路模擬器”DESSIS”來驗證研究分析結果。傳統平面電晶體發展成三維多閘極電晶體後遭遇到一些3D元件中固有的變化因素,3D元件模擬器是探討元件性能變化非常有用的工具。針對元件幾何形狀、摻雜濃度和器件物理效應的影響,3D模擬器被廣泛用於分析和優化元件特性,例如電位分佈(Potential Distribution),臨界電壓(Threshold Voltage),次臨界電流(Subthreshold Current),次臨界擺幅(Subthreshold Swing)和汲極導致能障降低(DIBL)。 此外,模擬器”DESSIS”結合電路模擬和元件模擬程式功能,可以進一步模擬次臨界邏輯電路(Subthreshold Logic Circuit)。本文關於多閘極金氧半場效電晶體的次臨界行為的研究不僅給提出了元件物理的見解,並且為次臨界邏輯電路設計和優化提供了基本方向,來防止性能下降和對製程變化的易感性,進而被應用於超低功率電路設計當中。
英文摘要 As growth in technology and development of mobile applications, wireless mesh networks, and other low power systems, the power consumption has become a critical concern in the circuit design. Recently, the ultra-low power digital circuits are rapidly gaining a wide interest owing to the increased problems of leakage currents, thermal management and reliability for all modern VLSI applications. It has been reported that subthreshold operation where the supply voltage is less than threshold voltage of the device, can reduce the energy significantly. Meanwhile, the scaling of gate length in conventional planar MOSFETs poses increasingly difficult challenges as leakage current and short-channel effects (SCEs) increase due to the decreasing control efficiency of the gate on the channel. To meet the above-mentioned problems, multi-gate (MG) device architecture in silicon-on-insulator (SOI) technology such as Double-Gate MOSFETs, Triple-Gate MOSFETs (FinFETs) and Gate-All-Around MOSFETs are proposed to minimize short-channel effects and extend the scaling of ultra-low power (ULP) MOSFETs into the nanometer regime. Up to now, although analog/AC behavior have been extensively investigated for static CMOS subthreshold logic circuits, there are very few papers focusing on the analysis of DC behavior, especially on the analysis of logic swing, noise margin and power consumption based on the device physics. Moreover, all of the mentioned-above literatures only put focus on the conventional planar MOSFET in investigating the subthreshold logic behavior, which can not suitable for the multi-gate (MG) MOSFET. Therefore, this thesis will focus on the subthreshold behavior analysis of multiple-gate MOSFETs that will apply to the logic circuit to explore logic characteristics.
In this thesis, based on the subthreshold behavior model of MG MOSFETs, we present the DC behavior model including logic swing, noise margin and average DC power consumption for the subthreshold logic circuit. The DC characteristics of subthreshold logic circuit are analyzed in depth. Since the model can be used for any logic style, the inverter is adopted as a reference circuit. Simple but accurate models of the MG MOSFETs operating in subthreshold region are first introduced. Then, the change of the DC characteristics due to ultra-low voltage operation is discussed in detail. Very low power dissipation can be achieved by ultra-low voltage operation. The price paid for the low power consumption is the reduced speed and dynamic range. However, the subthreshold logic gate primarily be used for applications in the ultra-low power end of the design spectrum. Therefore, the subthreshold circuit is suitable for certain applications (such as emerging wearable, smart cards, wireless sensors and other battery-operated applications like IoT) which do not require very high performance.
The mixed-mode circuit/device simulator “DESSIS” is used to validate the analytical results. Since a transition from conventional planar transistor to 3-D multiple-gate transistor has come with new sources of variability inherent in 3D device geometry, 3D device simulation can be a very useful tool to investigate the variability of device performance. 3D simulation is widely used to analyze and optimize device characteristics such as potential distribution, threshold voltage, subthreshold current, subthreshold swing and drain-induced barrier lowering (DIBL) due to changes in device geometry, doping concentration, and the effects of device physics. Furthermore, circuit and device equations have been merged, so that subthreshold logic circuits can be simulated. The research on the subthreshold behavior of multiple-gate transistors discussed in this thesis not only gives the physical insights into the device physics but also offers the basic guidance on subthreshold logic circuit design and optimization that can deter performance degradation and variations susceptibility. It can be effectively applied to the ultra-low power (ULP) circuits in the future.
論文目次 Abstract (Chinese) I
Abstract (English) III
Acknowledgements V
Contents VI
Table Captions X
Figure Captions XI

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Multiple-Gate MOSFETs 3
1.3 Subthreshold Logic Circuits 6
1.4 Organization of the Dissertation 8
Chapter 2 Quasi-3D Subthreshold Behavior Model for Junction-Based Trapezoidal
FinFETs 10
2.1 Introduction 10
2.2 Scaling Length Equation 12
2.3 Quasi-3D Subthreshold Potential Model 14
2.4 Minimum Conducting Channel Potential 20
2.5 Threshold Voltage Model 21
2.6 Subthreshold Current Model 27
2.7 Subthreshold Slope Model 30
2.8 Scaling Factor and Allowable Minimum Channel Length 34
2.9 Summary and Conclusions 36
Chapter 3 Quasi-3D Subthreshold Behavior Model for Junction-Based Double-Fin
Multi-Channel FETs with Localized Trapped Charges 37
3.1 Introduction 37
3.2 Scaling Length Equation 39
3.3 Threshold Voltage Model 44
3.4 Summary and Conclusions 55
Chapter 4 An Analytical DC Behavior Model of Junction-Based/Junctionless
Double Gate MOSFETs Applied for Subthreshold Logic Gates 56
4.1 Introduction 56
4.2 An Analytical DC Behavior Model of Junction-Based Double Gate
MOSFETs Applied for Subthreshold Logic Gates 57
4.2.1 Subthreshold Current Model 57
4.2.2 Equivalent Circuit Model 60
4.2.3 Logic Swing Model 61
4.2.4 Noise Margin Model 62
4.2.5 Average DC Power Consumption Model 65
4.2.6 Results and Discussion 69
4.3 An Analytical DC Behavior Model of Junctionless Double Gate
MOSFETs Applied for Subthreshold CMOS Inverter 77
4.3.1 Subthreshold Current Model 77
4.2.2 Equivalent Circuit Model 79
4.3.3 Logic Swing Model 80
4.3.4 Noise Margin Model 82
4.3.5 Average DC Power Consumption Mode 84
4.3.6 Results and Discussion 85
4.4 An Analytical DC Power Model of Junctionless Double Gate
MOSFETs Applied for Subthreshold NAND Gate 92
4.4.1 Model Derivation 92
4.4.2 Results and Discussion 97
4.5 Summary and Conclusions 101
Chapter 5 An Analytical DC Behavior Model of Junction-Based/Junctionless
Trapezoidal FinFETs Applied for Subthreshold Logic Gates 102
5.1 Introduction 102
5.2 An Analytical DC Behavior Model of Junction-Based Trapezoidal
FinFETs Applied for Subthreshold Logic Gates 104
5.2.1 Subthreshold Current Model 104
5.3.2 Equivalent Circuit Model 106
5.2.3 Logic Swing Model Derivation 108
5.2.4 Noise Margin Model Derivation 109
5.2.5 Average DC Power Consumption Model Derivation 111
5.2.6 Results and Discussion 112
5.3 An Analytical DC Behavior Model of Junctionless Trapezoidal
FinFETs Applied for Subthreshold Logic Gates 120
5.3.1 Subthreshold Current Model 120
5.3.2 Equivalent Circuit Model 122
5.3.3 Logic Swing Model Derivation 123
5.3.4 Noise Margin Model Derivation 124
5.3.5 Average DC Power Consumption Model Derivation 126
5.3.6 Results and Discussion 128
5.4 Summary and Conclusions 134
Chapter 6 An Analytical DC Behavior Model of Junction-Based/Junctionless
Quadruple Gate MOSFETs Applied for Subthreshold Logic Gates 136
6.1 Introduction 136
6.2 An Analytical DC Behavior Model of Junction-Based Quadruple Gate
MOSFETs Applied for Subthreshold Logic Gates 138
6.2.1 Subthreshold Current Model 138
6.2.2 Equivalent Circuit Model 140
6.2.3 Logic Swing Model Derivation 142
6.2.4 Noise Margin Model Derivation 143
6.2.5 Average DC Power Consumption Model Derivation 146
6.2.6 Results and Discussion 147
6.3 An Analytical DC Behavior Model of Junctionless Quadruple Gate
MOSFETs Applied for Subthreshold Logic Gates 155
6.3.1 Subthreshold Current Model 155
6.3.2 Equivalent Circuit Model 157
6.3.3 Logic Swing Model Derivation 158
6.3.4 Noise Margin Model Derivation 159
6.3.5 Average DC Power Consumption Model Derivation 161
6.3.6 Results and Discussion 162
6.4 Summary and Conclusions 170
Chapter 7 Conclusions and Future Works 171
7.1 Conclusions 171
7.2 Future Works 173
References 174
PUBLICATION LIST 185

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