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系統識別號 U0026-1408201101042900
論文名稱(中文) 應用於多標準/多模態可重組式共存系統之低功率高效能鎖相迴路
論文名稱(英文) The Low Power High Performance Phase-Locked Loop for the Multi-Standard/Multi-Mode Re configurable Co existence System
校院名稱 成功大學
系所名稱(中) 電機工程學系碩博士班
系所名稱(英) Department of Electrical Engineering
學年度 99
學期 2
出版年 100
研究生(中文) 林金龍
研究生(英文) Chin-Lung Lin
學號 n26981616
學位類別 碩士
語文別 中文
論文頁數 75頁
口試委員 指導教授-黃尊禧
口試委員-楊慶隆
口試委員-龎一心
口試委員-吳建華
口試委員-湯敬文
中文關鍵字 鎖相迴路  低功率  四相位  真實單相時脈  電流模式邏輯 
英文關鍵字 PLL  low power  quadrature  TSPC  CML 
學科別分類
中文摘要 本論文主要是在設計一個應用於多標準/多模態可重組式共存系統之低功率高效能鎖相迴路的鎖相迴路;並利用TSMC 90-nm RF CMOS和TSMC 0.18-μm RF CMOS製程技術分別實現此鎖相迴路電路晶片及本實驗室所提出的新式真實單相時脈四相位除三電路的電路晶片。針對載波系統整合進行初步的四相位載波輸出鎖相迴路設計,以低功率高效能作為主要達成目標。整體鎖相迴路的子電路包含了一個操作頻率在6.4-GHz到7.8-GHz的可調式變壓器耦合互補式四相位壓控振盪器、一個採用兩個電流模式(CML)邏輯除二電路所組成的除四電路、一個由本實驗室所提出的新式真實單相時脈四相位除三電路、一個利用預充型D型正反器所組成的相位頻率偵測器、一個利用誤差放大器降低電流的誤差及減低非理想效應的充電幫浦電路。
首先論文內容會先提到本實驗室所提出的新式真實單相時脈四相位除三電路的電路特點。在現今的除三電路架構中擁有四相位輸出的除三電路並不多見,且相較於傳統類比Miller除三電路,此新式真實單相時脈四相位除三電路大幅降低電路複雜度和核心功率消耗。由於此電路為一個四相位輸入四相位輸出的除三電路,在量測上提供四相位輸入訊號較為困難,因此為了驗證除三電路的功能性,電路整合一個互補式LC tank 壓控振盪器及一個電流模式邏輯的除二電路。由於電流模式邏輯的除二電路為一個四相位輸出的電路,故可以供給真實單相時脈四相位除三電路的輸入訊號作除頻的動作,以避免設計被動式四相位電路產生不易匹配的問題。此整體電路將使用TSMC 0.18-μm RF CMOS製程技術來實現;在量測結果方面,電流模式邏輯除二電路消耗功率約為2.4mW,而新式真實單相時脈四相位除三電路消耗功率約為12.79mW;整體電路消耗功率約為40.68mW,晶片面積約為1.65×1.16 mm2。
在多標準/多模態可重組式共存系統之低功率高效能鎖相迴路的鎖相迴路設計方面,我們把新式真實單相時脈四相位除三電路及電流模式邏輯的除二電路組成預除器實現在此鎖相迴路。本鎖相迴路方面,參考訊號頻率為594MHz,鎖定頻率為7,128MHz,鎖定時間約為1.5μs,Reference Spur約為-69dBm,整體鎖相迴路電路消耗功率約為32.72mW,整體佈局面積約為1.895×1.59 mm2。
英文摘要 The main part of this thesis is to design a low power high performance phase-locked loop for the multi-standard/multi-mode re-configurable co-existence system. Fabricated in TSMC’s 90-nm RF CMOS process, an integrated carrier generator system is designed for a phase locked loop with quadrature outputs, low-power high-performance. The whole PLL with an operating frequency in the band from 6.4GHz to 7.8GHz includes a transformer-coupled complementary QVCO, a divide-by-four circuit consisting of two current mode logic (CML) divide-by-two circuits, a novel true single phase clocked (TSPC) divide-by-three circuit, a phase frequency detector consisting of precharged type D flip-flops, and an error amplifier to reduce the current mismatch and the non-ideal effects of the charge pump circuit.
First, a novel TSPC divide-by-three circuit design is mentioned. Today divide-by-three circuits with quadrature outputs are not reported so often, as compared to traditional analog miller divide-by-three circuits. Our novel TSPC divide-by-three circuit significantly reduces the circuit complexity and power consumption of the UWB frequency synthesizer , since the novel TSPC divide-by-three circuit is a circuit with quadrature inputs and quadrature outputs . The measurement of the divider is more difficult for providing matched quadrature input signals from external boluns. Therefore, to easily verify the divider circuit function, the whole circuit has been integrated with a complementary LC tank VCO and a current-mode logic divide-by-two circuit. Since a current-mode logic divide-by-two circuit is a circuit that can provide quadrature outputs, it can provide the quadrature input signals to the TSPC divide-by-three circuit. The whole circuit has been fabricated in TSMC 0.18-μm RF CMOS process. From the measurement data shown, the power consumption of current mode logic divide-by-two circuit is about 2.4mW. The power consumption of true single phase clocked divide-by-three circuit is 12.79mW. The total power consumption is about 40.68mW. The chip area is about 1.65×1.16 mm2.
In our designed phase-locked loop, the prescaler circuit consists of the TSPC divide-by-three circuit and current-mode logic divide-by-two circuit. In the simulation results of this phase locked loop, the frequency of reference signal is 594MHz.The locked frequency is 7,128MHz, and the locked time is about 1.5μs. The simulated reference spur is -69dBm, While total power consumption is about 32.72mW. The layout area of chip is about 1.895×1.59 mm2.
論文目次 摘要 I
Abstract III
誌謝 V
目錄 VII
表目錄 IX
圖目錄 X
第一章 緒論 1
1.1研究背景與動機 1
1.2論文架構 2
第二章 新式真實單相時脈四相位除三電路 3
2.1壓控振盪器的設計 3
2.1.1 環形振盪器 3
2.1.2 LC壓控振盪器 4
2.2電流模式邏輯除二電路 10
2.3新式真實單相時脈四相位除三電路 12
2.4電路模擬結果 17
2.4.1互補式LC壓控振盪器模擬結果 17
2.4.2 整體電路模擬結果 20
2.5 電路量測結果 22
2.5.1量測結果 22
第三章 鎖相迴路設計 29
3.1架構簡介 29
3.1.1頻率合成器整體架構 29
3.1.2 PLL架構 30
3.2 變壓器耦合互補式四相位壓控振盪器 31
3.3 相位頻率偵測器(Phase Frequency Detector, PFD) 37
3.4 充電幫浦(Charge Pump, CP) 43
3.5 低通迴路濾波器(Low Pass Filter, LPF) 50
3.6 除頻器(Divider) 60
3.7 PLL電路模擬結果 63
第四章 結論與未來規劃 71
4.1結論 71
4.2未來規劃 72
參考文獻 73
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