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系統識別號 U0026-1311201711593900
論文名稱(中文) 多物件偵測射頻標籤之整流穩壓電路和鎖相迴路設計
論文名稱(英文) Regulated Rectifier Circuit and Phase-Locked Loop Design for Multi-Object Detection RF Tag
校院名稱 成功大學
系所名稱(中) 電機工程學系
系所名稱(英) Department of Electrical Engineering
學年度 106
學期 1
出版年 106
研究生(中文) 黃安慶
研究生(英文) An-Ching Huang
學號 n26041351
學位類別 碩士
語文別 中文
論文頁數 102頁
口試委員 召集委員-黃世杰
指導教授-黃尊禧
口試委員-楊慶隆
口試委員-鄭光偉
中文關鍵字 自供電射頻標籤  寬頻匹配網路  帶差能隙參考電路(Bandgap)  低壓降線性穩壓器(LDO)  低壓降鎖相迴路 
英文關鍵字 Self power RF Tag  brodband matching network  Bandgap voltage reference  Low dropout linear regulator(LDO)  Low voltage PLL 
學科別分類
中文摘要 應用諧波雷達技術實行無線傳能與多物件偵測已成為現今廣泛應用於生醫領域與IOT之技術,其特點為利用目標物對電磁波的反射波而發現目標,並且測定出目標之相對距離與相對位置,將這些所得的訊號經過訊號處理以得到所需要之資訊。其中射頻獵能電子更是新興的領域。其主要訴求是透過天線,從環境中擷取微弱的射頻能量,來供給電力給予後級電路使用,再進一步透過輸出端天線發射能量,以同時達到無線傳能與綠能之效果。
本論文為了實現自我供電(self-power)的設計,低電壓的設計成為本論文的核心目標之一,進而達到降低前端整流電路的輸入功率需求。本論文提出一應用於多物件偵測之RF-DC整流穩壓電路與4.8GHz的鎖相迴路,藉由耦極天線接收2.4 GHz之RF訊號,一方面將RF整成DC直流後分別供給帶差參考電路(Bandgap)與低壓降線性穩壓器(LDO)穩壓後轉成穩定之1.2V DC直流,以供給後方之鎖相迴路(PLL)使用。另一方面偶極天線接收之2.4 GHz RF訊號經過降頻後轉成70.5 MHz以做為鎖相迴路(PLL)之參考頻率。
其中在RF轉DC之部份先使用實驗室開發的程式輔助設計PCB板的寬頻匹配網路以提高傳輸效率並使用全波整流器將輸入訊號轉成DC直流。DC-DC之Bandgap部份考慮到獵能系統講求低功耗的部份,使用MOS操作在 weak inversion的方式使電路來達到低功耗下同時擁有抗溫度係數之能力。LDO的部份是為了提供PLL之子電路乾淨穩定之DC電源,並隔離數位與類比及RF電路之電源,使之不會互相干擾,本系統中使用了三個LDO,其目的為隔離PLL各子電路電源端之間的干擾,以防止像是VCO等RF電路與PFD及Divider等數位電路以及如Charge Pump類比電路間電源的互相干擾。
在多物件偵測系統中為了待測物之間不產生互相干擾,本論文之鎖相迴路輸出頻率定為4.8 GHz附近,並藉由在PLL中之壓控振盪器(VCO)與除頻器(Divider)做控制以達到切頻的功能,使PLL輸出頻率可做4.512 GHz、4.794 GHz、5.076 GHz之頻率切換。其中VCO使用互補式LC-tank VCO搭配二位元之電容切換陣列以降低功率消耗並增加頻率可調範圍。Divider方面先以CML除頻器(Current Mod Logic)以達到高頻訊號之除頻,其後藉由DTS(Differential to Single)將Differential訊號轉成Single再供給TSPC除頻器(True Single-Phase Clock)做除頻,最後交給二位元控制位元之多模態除頻器做除數(16、17、18)之切換,以達到切頻之目的。工作電壓定為1.2V以降低操作功率消耗。
以上所述之所有晶片電路皆是使用台積電所提供之 TSMC 0.18-μm CMOS 製程。本論文將依序詳細介紹以上晶片之電路架構以及其模擬與量測結果。
英文摘要 In order to realize the design of self-powered, the circuit and system of low voltage design become the main purpose of the thesis. In this thesis, a RF-DC converter circuit and a 4.8 GHz phase-lock loop for multi-object detection are proposed. The detection system of human thoracic breathing heartbeat consists of three blocks, a transmitter, a receiver and a RF tag. To detect the object, the transmitter begins to transmit 2.4 GHz RF signal to the RF tag. The received 2.4 GHz RF signal is rectified by a rectifier into the DC value of 1.5V which is then applied as the supply voltage to of the bandgap voltage reference circuit and low voltage drop linear regulator (LDO). The output voltage of the LDO provides a stable 1.2V DC supply to the 4.8 GHz phase-locked loop (PLL) circuits. Part of the received 2.4 GHz RF signal is also divided into a frequency as reference signal and phase modulation input to the phase detector of the 4.8 GHz PLL, the modulated 4.8 GHz signal is then amplified and re-transmitted to the receiver of the detection system.
In the RF-DC rectification design, a program-assisted broadband matching network on PCB which developed in our laboratory is used to improve the rectification efficiency of the full-wave rectifier to rectify RF signal into 1.5V DC voltage. In the design of bandgap voltage reference circuit in the DC-DC converter, the low power consumption is the main concern, therfore, the weak inversion MOS operation is adopted to achieve low power consumption while having to resist the temperature variation. There are three LDO implemented in PLL, the purpose is to provide clean and stable DC power supply to the PLL circuits and also to isolate the power supply of RF circuits (such as VCO), digital circuits (such as PFD and divider) and analog circuits (such as charge pump) from being interfered with each other.
In the phase-lock loop circuit for multi-object detection, the output frequency of the phase-locked loop is design at 4.8 GHz, in order to make the objects not to interfere with each other, the control bits of voltage-controlled oscillator (VCO) and the frequency divider are varied to change the PLL output frequency, so that the PLL output frequency can be selected at 4.512 GHz, 4.794 GHz, and 5.076 GHz. The VCO uses complementary LC-tank with two bits capacitor switching array to reduce power consumption and also to increase the frequency tuning range. In the frequency divider, first stage uses CML (Current Mod Logic) frequency divider for high frequency division, a DTS is then used to convert the differential signal to single-ended signal, which is then connected to the TSPC (True Single -Phase Clock) frequency divider at 1.2 GHz. The last divider is a two bits control bits of the multi-modal digital frequency divider with three different divisors (16, 17, 18) to switch between the required frequencies.
All of the circuits described above are fabricated with TSMC 0.18-μm CMOS processes. In this thesis, simulation and measurement results of the above-mentioned circuits will be described in detail in this thesis.
論文目次 第一章 緒論 1
1.1 前言 1
1.2 研究動機 2
1.3 論文架構概述 5
第二章 RF-DC 整流穩壓轉換電路 9
2.1 RF-DC 整流穩壓轉換電路 9
2.2匹配網路與整流器(Matching and Rectifier) 10
2.3帶差參考電路(Bandgap) 13
2.3.1 低電壓低功耗之帶差參考電路 14
2.3.2 本論文使用之帶差參考電路 15
2.4低壓降線性穩壓器(Low Dropout Linear Regulator,LDO) 18
2.4.1 基本工作原理 19
2.4.2 頻率響應與穩定度分析 20
2.4.3 設計相關考量 23
2.4.4 本論文使用之低壓降線性穩壓器 24
第三章 4.8 GHz鎖相迴路設計(Phase Locked Loop) 26
3.1 鎖相迴路設計 26
3.2 相位頻率偵測器(Phase Frequency Detector,PFD) 27
3.2.1 相位頻率偵測器非理想性 27
3.2.2 本系統所使用之相位頻率偵測器 29
3.3 電荷幫浦(Charge Pump, CP) 31
3.3.1 電荷幫浦之非理想性 31
3.3.2 本系統之電荷幫浦架構 35
3.4 壓控振盪器(Voltage Controlled Oscilloator,VCO) 36
3.4.1 壓控振盪器原理 36
3.4.2 切換電容陣列壓控振盪器 40
3.5 除頻器(Frequency Dividers) 43
3.5.1 電流模式除頻器(Current Mode Logic, CML ) 43
3.5.2 真單相時脈除頻器(True Single Phase Clock, TSPC ) 46
3.5.3 三模除頻器(Triple Modulus Frequency) 47
第四章 模擬與量測 51
4.1 180 ̊ Hybrid Ring模擬與量測 53
4.2 整流器(Rectifier)模擬與量測 56
4.2.1 整流器(Rectifier)模擬設計與匹配網路設計 57
4.2.2 整流器(Rectifier) 模擬與量測數據 60
4.3 帶差參考電路(Bandgap)模擬與量測 64
4.3.2 帶差參考電路(Bandgap)特性模擬 64
4.3.3 帶差參考電路(Bandgap)量測數據 65
4.4 線性穩壓器(LDO)模擬與量測(不包含Bandgap) 67
4.4.1 線性穩壓器(LDO)模擬 67
4.4.2 線性穩壓器(LDO)量測數據 71
4.5 鎖相迴路(PLL)模擬與量測 75
4.5.1 鎖相迴路(PLL)之子電路模擬與量測 75
4.5.2 鎖相迴路(PLL)系統模擬與量測 83
4.6 整體系統模擬與量測 89
4.6.1 RF-DC 整流穩壓電路整體系統模擬與量測 89
4.6.2 RF-DC整流穩壓電路與鎖相迴路(PLL)整合模擬 93
第五章 結論與未來規劃 97
5.1結論 97
5.2 未來規劃 98
參考文獻 99

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