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系統識別號 U0026-1308202015260400
論文名稱(中文) 一個嵌入於連續漸進逼近式類比數位轉換器之物理不可複製函數的晶片設計
論文名稱(英文) Chip Design of a Physically Unclonable Function Embedded in a SAR ADC
校院名稱 成功大學
系所名稱(中) 電機工程學系
系所名稱(英) Department of Electrical Engineering
學年度 108
學期 2
出版年 109
研究生(中文) 陳奕穎
研究生(英文) Yi-Ying Chen
學號 N26074655
學位類別 碩士
語文別 英文
論文頁數 73頁
口試委員 指導教授-張順志
口試委員-許孟烈
口試委員-魏嘉玲
口試委員-蔡建泓
口試委員-邱瀝毅
中文關鍵字 連續漸進逼近式類比數位轉換  物理不可複製函數  挑戰-響應對  物聯網 
英文關鍵字 Successive-Approximation Register Analog-to-Digital Converter (SAR ADC)  Physically Unclonable Function (PUF)  Challenge-Response Pair (CRP)  Internet of Things (IoT) 
學科別分類
中文摘要 本論文提出一個嵌入於十位元的連續漸進逼近式類比數位轉換器之物理不可複製函數(Physically Unclonable Function),本論文提出之晶片有兩種工作模式:物理不可複製函數模式和類比數位轉換器模式。在物理不可複製函數模式下,此功能通過操縱類比數位轉換器中的電容器陣列來實現物理不可複製函數的功能,而且只需要極少的面積代價。本論文採用漂移消除電路(Offset Cancellation Circuit)來改善物理不可複製函數的均勻性(Uniformity),並使用挑戰-響應對(Challenge Response Pairs)做為物理不可複製函數的驗證機制,挑戰-響應對的可靠性(Reliability)和獨特性(Uniqueness)分別為97.69%和48.1%,挑戰-響應對的均勻性為50.59%,非常接近理想值50%。在ADC模式中,此設計在20 MS / s下有效位元數可達到9.66。
英文摘要 This thesis presents a physically unclonable function (PUF) embedded in a 10-bit successive-approximation register (SAR) analog-to-digital converter (ADC). There are two operation modes in this design: PUF mode and ADC mode. In the PUF mode, this design realizes the physically unclonable function by manipulating the capacitor array in the SAR ADC. Only a little area overhead is required for implementing the PUF. An offset cancellation circuit is employed to improve the uniformity of the PUF design. The proposed PUF is authenticated using Challenge Response Pairs (CRPs). Reliability and Uniqueness of the CRPs are 97.69% and 48.1%, respectively. Uniformity of the CRPs is 50.59% that is very close to the ideal value of 50%. In the ADC mode, this design achieves an ENOB of 9.66 under 20 MS/s.
論文目次 摘 要 I
Abstract II
List of Tables VI
List of Figures VII
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Organization of the Thesis 3
Chapter 2 Background Knowledge of Physical Unclonable Function 4
2.1 Challenge-and-Response Authentication Protocol 4
2.2 Concept of Physical Unclonable Function 7
2.3 Category of Physical Unclonable Function 8
2.3.1 Memory-based PUF 8
2.3.2 Delay-based PUF 9
2.3.3 Anti-Fuse PUF 12
2.3.4 Analog PUF 15
Chapter 3 A Physically Unclonable Function Embedded in a SAR ADC 22
3.1 Bottleneck of PUF 22
3.2 The Architecture of Proposed ADC PUF 26
3.3 Circuit-Level Design 30
3.3.1 Capacitive DAC 30
3.3.2 Dynamic Comparator 34
3.3.3 PUF Control and DAC Buffer 39
3.3.4 Bootstrapped Switch 41
3.3.5 Digital Control Logic Circuit 44
Chapter 4 Simulation and Measurement Results 46
4.1 Layout and Chip Floor Plan 46
4.2 Parameter of PUF Performance 48
4.3 Simulation Result 52
4.3.1 Post-layout simulation of PUF 52
4.3.2 Post-layout simulation of SAR ADC 54
4.4 Die Micrograph and Measurement Setup 56
4.5 Measurement Results 58
4.5.1 Measurement of PUF 58
4.5.2 Measurement of SAR ADC 62
Chapter 5 Conclusions and Future Work 65
Bibliography 67
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