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系統識別號 U0026-1308201411464900
論文名稱(中文) 根據基因演算法之金屬氧化物半導體電容陣列產生器
論文名稱(英文) MOS Capacitor Array Generator based on Genetic Algorithm
校院名稱 成功大學
系所名稱(中) 電機工程學系
系所名稱(英) Department of Electrical Engineering
學年度 102
學期 2
出版年 103
研究生(中文) 蔡榮陽
研究生(英文) Rung-Yang Tsai
學號 n26011403
學位類別 碩士
語文別 中文
論文頁數 47頁
口試委員 指導教授-林家民
口試委員-李毅郎
口試委員-趙家佐
口試委員-陳東傑
口試委員-江哲維
中文關鍵字 電容陣列電路擺置  類比電路繞線  佈局自動化 
英文關鍵字 capacitor placement  analog routing  layout automation 
學科別分類
中文摘要 大部分類比電路的佈局仍透過人工進行置及繞線,工作相當繁瑣且耗費時間,因此電路實體自動化一直是大家希望解決的問題,希望藉由程式的協助快速考慮電路連線關係完成擺置及繞線並整合於晶片,可減少工程師重新規劃電路擺置及繞線的時間。電容是類比電路中常用的原件且廣泛的應用在電路上。IC中常用到的電容架構為MIM、MOS…等,MIM電容單位面積容值小精確度高,花費面積較大,可應用於類比轉數位或數位轉類比電路上;MOS電容單位面積容值大精確度與MIM架構相比較低,花費面積較小,可應用於震盪器及穩壓電路上。大部分的自動化方法著重在MIM電容陣列,較少的文獻是討論MOS電容陣列,在震盪器電路中,藉由使用MOS電容陣列調整容值並減少面積的消耗。我們採用基因演算法實作MOS電容陣列四個方向都有電容的對外接點,考慮繞線線長及是否有線段互相重疊而需轉換金屬層,進行內部單位電容的擺置,並使用歷歷史基底迷宮繞線完成後續的繞線,因較少文獻探討此問題,我們使用貪婪演算法來進行擺置,從實驗結果中顯示我們的演算法在有效的執行時間內,線長及金屬層的使用都比貪婪擺置方法更加有效。
英文摘要 With the process of semiconductor technology, there are more and more transistors on a single chip. Most of layouts are completed manually, which is tedious and time-consuming. If some analog layout can be implemented by an automatic tool, the design time can be reduced. A capacitor array is an important component in analog designs, which is widely used in many circuits such as switch-capacitor circuit. And the layout styles of capacitor arrays are similar to row-based designs in digital circuits. There exist two kinds of capacitor arrays as follows: MIM capacitor and MOS capacitor. An MIM capacitor is built by two parallel plates and it has lower capacitance density but higher area. It can apply to digital-to-analog converts (DACs) circuits and analog-to-digital converts (ADCs) circuits. An MOS capacitor is built by a MOSFET and shorted the drain and source in MOSFET. It has higher capacitance density but lower area. It can apply to oscillator and regulator. Some automation methodology about MIM capacitor array has been proposed. There exist limited research about MOS capacitor array automation. This is the first thesis implements the MOS capacitor array used in the oscillator circuit. We considers the output pins at each side in the MOS capacitor array to use fewer wire length and metal layer. And we adopt the genetic algorithm to deal with the overall placement. In our algorithm flow, first, we checking feasibility of capacitor array. Second, we adopt genetic algorithm to perform our placement. Finally, we use the history-based maze routing to connect the connections. After the placement and routing, we can integrate into a real design and satisfy the DRC and LVS check. In the experimental results, we implemented our capacitor layout generation algorithm in the C++ programming language and perform the layout automatically on Laker platform. Because of limited research focus on MOS capacitor array. We use the greedy algorithm to perform placement. And use it to compare with our genetic placement. In experimental result show that our proposed approach can use fewer wire length and metal layer to complete the circuits.
論文目次 摘要 i
誌謝 viii
目錄 ix
圖片目錄 xii
1. 序論 1
1.1 動機 1
1.2 金屬氧化物半導體電容 2
1.3 相關研究 4
1.3.1 電容陣列擺置演算法 9
1.3.2 電容陣列繞線演算法 10
1.4 研究貢獻 12
2. 問題描述 13
2.1 輸入資訊 14
2.2 問題目標 14
2.3 限制條件 14
3. 設計流程 15
4. 檢查合理之陣列維度 16
5. 擺置演算法 18
5.1 基因演算法 18
5.1.1 染色體對應電容陣列表示法 19
5.1.2 基因擾動 20
5.1.3 計算染色體身體素質 23
5.2 建立對外接點 25
6. 繞線演算法 29
6.1 保護環內單位電容之連線 30
6.2 歷史基底的三維立體迷宮繞線 31
6.2.1 三維立體繞線圖 31
6.2.2 三維立體迷宮繞線 32
6.2.3 拆除與重繞 34
7. 實驗結果 35
8. 結論 45
參考文獻 46
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[7] P. Min, and C. Chu, "FastRoute 2.0: A High-quality and Efficient Global Router." pp. 250-255.
[8] Y. Zhang, Y. Xu, and C. Chu, “FastRoute3.0: a fast and high quality global router based on virtual capacity,” in Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, San Jose, California, 2008, pp. 344-349.
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[13] L. Wen-Hao, and L. Yih-Lang, “Optimizing the Antenna Area and Separators in Layer Assignment of Multilayer Global Routing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 4, pp. 613-626, 2014.
[14] L. McMurchie, and C. Ebeling, “PathFinder: a negotiation-based performance-driven router for FPGAs,” in Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, Monterey, California, USA, 1995, pp. 111-117.
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