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系統識別號 U0026-1308201410405700
論文名稱(中文) 針對全客戶設計數位電路能考量設計規則驗證之細部繞線器
論文名稱(英文) DRC Aware Detailed Router for Digital Circuits in Full-Custom Design
校院名稱 成功大學
系所名稱(中) 電機工程學系
系所名稱(英) Department of Electrical Engineering
學年度 102
學期 2
出版年 103
研究生(中文) 王郁仁
研究生(英文) Yu-Ren Wang
學號 n26011291
學位類別 碩士
語文別 中文
論文頁數 38頁
口試委員 指導教授-林家民
口試委員-李毅郎
口試委員-趙家佐
口試委員-陳東傑
口試委員-江哲維
中文關鍵字 細部繞線  繞線擁塞  佈局自動化 
英文關鍵字 detailed routing  routing congestion  layout automation 
學科別分類
中文摘要 隨著製程技術的發展,電晶體單位密度的提升使得單一晶片可以容納更多的電路,同時也為實體設計的過程帶來更多的挑戰。隨著電路的複雜度不斷地增加,繞線階段所消耗的時間在整個晶片實體化的比例越來越高,使得如何有效率地進行繞線變成相當重要的議題。目前全客戶設計的電路涵蓋數位及類比兩個部分,一般皆由佈局工程師進行人工的擺置及繞線,其中數位電路的部分其元件數及連線數往往遠大於類比電路,因此佈局設計所需消耗的時間及品質非常依賴設計者的經驗與判斷,然而即使是有相當經驗的工程師仍然需要花費相當多的時間進行佈局。因此,本論文針對全客戶設計的數位電路提出一個繞線自動化的設計流程,在給定的擺置下,同時考量繞線擁塞與線長進行繞線,可以同時考量到所有的連線並合理的分配繞線資源,並在滿足製程的設計規則下,完成所有的繞線。經由實驗結果可以看到程式執行的時間相較於人工進行佈局所花費的時間也有顯著的提升。將整個流程以C++及Tcl/Tk實現,並在Synopsys® Laker3™上自動產生繞線結果。
英文摘要 Due to the increasing complexity of designs, it spends more and more time in routing in the physical design flow. Compared to analog circuits, size of digital circuits in full-custom design is larger, which requires more effort in placement and routing. Thus, this thesis focuses on the routing problem in full-custom digital circuits. We adopt the grid-based routing model to route nets because it is simple and easy to handle DRC rules. Similar to NTHU-Route 2.0, our routing algorithm is composed of four stages. In the initial stage, we project a multilayer design on to a 2D plane, and then perform 2D routing followed by the layer assignment. In the main stage, the solution is improved by using the rip-up and reroute method. This stage adopts 3D multi-source multi-sink maze routing with the history base cost function to route nets. The refinement stage focuses on finding a short-free path for every short net by using different cost function. Finally, some segments are shifted to attach the pins in layout for resolving the DRC violations in the legalization stage. Our detailed router was implemented in the C++ programming language and the routing result was displayed on Laker3®. Experimental results shows our routing method can pass LVS check and minimize the number of DRC violations.
論文目次 摘要 i
誌謝 v
目錄 vi
表目錄 viii
圖目錄 ix
第1章 緒論 1
1.1. 繞線問題 2
1.2. 相關研究介紹 4
1.3. 研究貢獻 7
1.4. 論文架構 8
第2章 問題描述 9
第3章 相關背景 11
3.1. 多重起點多重終點迷宮繞線法 11
3.2. NTHU-Route 2.0 13
第4章 考量設計規則之細部繞線 18
4.1. 細部繞線器架構 18
4.2. 初始繞線結果之建立 19
4.3. 多重起點多重終點三維迷宮繞線法 21
4.4. 繞線順序及參數調整 23
4.5. 單一訊號接點多重連接點 24
4.6. 設計規則合法化 25
第5章 實驗結果 29
第6章 結論 35
第7章 參考論文 36
參考文獻 [1] L. Cheng-Wu, L. Cheng-Chung, H. Chun-Po, C. Soon-Jyh, and L. Jai-Ming, "Routing-aware placement algorithms for modern analog integrated circuits," in Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on, 2011, pp. 1-4.
[2] L. Cheng-Wu, L. Chung-Lin, L. Jai-Ming, and C. Soon-Jyh, "Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits," in Computer-Aided Design (ICCAD), 2012 IEEE/ACM International Conference on, 2012, pp. 635-642.
[3] O. Hung-Chih, C. Hsing-Chih Chang, and C. Yao-Wen, "Non-uniform multilevel analog routing with matching constraints," in Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE, 2012, pp. 549-554.
[4] C.-W. Lin, C.-C. Lu, J.-M. Lin, and S.-J. Chang, "Routability-driven placement algorithm for analog integrated circuits," presented at the Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design, Napa, California, USA, 2012.
[5] M. M. Ozdal and R. F. Hentschke, "Maze routing algorithms with exact matching constraints for analog and mixed signal designs," in Computer-Aided Design (ICCAD), 2012 IEEE/ACM International Conference on, 2012, pp. 130-136.
[6] R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, "Pattern routing: use and theory for increasing predictability and avoiding coupling," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 21, pp. 777-790, 2002.
[7] P. Min and C. Chu, "FastRoute 2.0: A High-quality and Efficient Global Router," in Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific, 2007, pp. 250-255.
[8] C. Y. Lee, "An Algorithm for Path Connections and Its Applications," IEEE Transactions on Electronic Computers, vol. EC-10, pp. 346-365, 1961.
[9] J. A. Roy and I. L. Markov, "High-performance routing at the nanometer scale," in Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on, 2007, pp. 496-502.
[10] P. Min and C. Chu, "FastRoute: A Step to Integrate Global Routing into Placement," in Computer-Aided Design, 2006. ICCAD '06. IEEE/ACM International Conference on, 2006, pp. 464-471.
[11] Z. Yanheng, X. Yue, and C. Chu, "FastRoute3.0: A fast and high quality global router based on virtual capacity," in Proc. ICCAD, 2008, pp. 344-349.
[12] X. Yue, Z. Yanheng, and C. Chu, "FastRoute 4.0: Global router with efficient via minimization," in Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific, 2009, pp. 576-581.
[13] M. M. Ozdal and M. D. F. Wong, "Archer: A History-Based Global Routing Algorithm," Ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, pp. 528-540, Apr 2009.
[14] Y.-J. Chang, Y.-T. Lee, J.-R. Gao, P.-C. Wu, and T.-C. Wang, "NTHU-Route 2.0: A Robust Global Router for Modern Designs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, pp. 1931-1944, 2010.
[15] W.-H. Liu, W.-C. Kao, Y.-L. Li, and K.-Y. Chao, "NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, pp. 709-722, 2013.
[16] C. Huang-Yu, H. Chin-Hsiung, and C. Yao-Wen, "High-performance global routing with fast overflow reduction," in Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific, 2009, pp. 582-587.
[17] S. Hyunchul and A. Sangiovanni-Vincentelli, "A Detailed Router Based on Incremental Routing Modifications: Mighty," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 6, pp. 942-955, 1987.
[18] L. Youn-Long, H. Yu-Chin, and T. Fur-Shing, "SILK: a simulated evolution router," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 8, pp. 1108-1114, 1989.
[19] J. Cong, F. Jie, and K. Kei-Yong, "DUNE-a multilayer gridless routing system," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, pp. 633-647, 2001.
[20] C. Yao-Wen and L. Shih-Ping, "MR: a new framework for multilevel full-chip routing," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 793-800, 2004.
[21] H. Kuan-Hsien, O. Hung-Chih, C. Yao-Wen, and T. Hui-Fang, "Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits," in Design Automation Conference (DAC), 2013 50th ACM / EDAC / IEEE, 2013, pp. 1-6.
[22] Y. Hailong, C. Yici, and G. Qiang, "LEMAR: A novel length matching routing algorithm for analog and mixed signal circuits," in Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific, 2012, pp. 157-162.
[23] M. M. Ozdal and R. F. Hentschke, "Exact route matching algorithms for analog and mixed signal integrated circuits," in Computer-Aided Design - Digest of Technical Papers, 2009. ICCAD 2009. IEEE/ACM International Conference on, 2009, pp. 231-238.
[24] C. Chu, "FLUTE: fast lookup table based wirelength estimation technique," in Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on, 2004, pp. 696-701.
[25] L. McMurchie and C. Ebeling, "PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs," in Field-Programmable Gate Arrays, 1995. FPGA '95. Proceedings of the Third International ACM Symposium on, 1995, pp. 111-117.
[26] C. Tung-Chieh, J. Zhe-Wei, H. Tien-Chang, C. Hsin-Chen, and C. Yao-Wen, "NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 27, pp. 1228-1240, 2008.
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