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系統識別號 U0026-1208202016085800
論文名稱(中文) 以Matlab/Simulink模型化基礎設計快速實作數位降壓型轉換器
論文名稱(英文) Rapid Implementation of Digital Buck Converter with Matlab/Simulink Model-Based Design
校院名稱 成功大學
系所名稱(中) 電機工程學系
系所名稱(英) Department of Electrical Engineering
學年度 108
學期 2
出版年 109
研究生(中文) 趙文彥
研究生(英文) Wun-Yan Jhao
學號 N26061432
學位類別 碩士
語文別 中文
論文頁數 110頁
口試委員 指導教授-蔡建泓
口試委員-張順志
口試委員-楊峻泓
口試委員-李大輝
口試委員-莊明男
中文關鍵字 數位控制降壓型轉換器  模型化基礎設計  Fixed Point Designer  HDL Coder  HDL Co-Simulation  FPGA-in-the-Loop 
英文關鍵字 Buck converter  Model Based Design  Fixed Point Designer  HDL Coder  HDL Co-Simulation  FPGA-in-the-Loop 
學科別分類
中文摘要 本論文使用模型化基礎設計實現數位控制降壓型電源轉換器,在不撰寫HDL程式碼的前提下,使用Matlab/Simulink所提供之硬體模型及其工具(Fixed Point Designer、HDL Coder)進行數位控制器設計及HDL程式碼(Verilog)自動生成,在系統建模階段,為了找出最適合用來快速實作的硬體模型,因此針對編碼器及PID補償器的部份將提出多種方式來實現,並根據實現方法及其FPGA使用資源來決定最適合應用在快速實作的建模方法。
本設計以HDL Co-Simulation及FPGA-in-the-Loop進行模擬驗證,在確認系統模擬正確且符合規格後,將透過FPGA快速原型化進行系統量測,本論文採用目前主流的Xilinx及Intel FPGA實現數位控制器並分別進行量測驗證,透過合成結果顯示,HDL Coder所生成之HDL程式碼其FPGA使用資源數與傳統人工設計結果幾乎一致,透過量測結果顯示,該設計方法所設計的數位控制器能有效控制系統,最後透過台灣積體電路製造股份有限公司所提供之 0.18-μm 1P6M CMOS製程將其整合並做成晶片。
英文摘要 In this thesis, Adopt model based design to implement a digitally controlled buck converter. In the system verification, the current mainstream FPGAs are used for system verification, and using TSMC 0.18-μm 1P6M CMOS process to integrate it and makes it into a chip. In addition to the external inductance and capacitance, the rest of the circuits are integrated in the chip.
Under the premise of not writing any HDL code, use the hardware model and tools (Fixed Point Designer、HDL Coder) provided by Matlab/Simulink to design the digital controller and automatically generate HDL code (Verilog), In the system modeling stage, in order to find the most suitable hardware model for rapid implementation, a variety of methods will be proposed for the encoder and PID compensator. Finally, according to the implementation method and the FPGA resource usage Decide which modeling method is most suitable for rapid implementation, In the system simulation stage, HDL Co-Simulation and FPGA-in-the-Loop are used for simulation verification. After confirming that the system simulation is correct and meets the specifications, system measurement and chip synthesis will be implemented through FPGA rapid prototyping and Synopsys-Design Compiler
Model based design can effectively avoid coding errors caused by manual coding. Moreover, according to TeraSoft survey results, after using this design method, not only find more bugs from model simulation, but also enable the team to implement rapid prototyping of FPGAs is faster than the traditional manual workflow.
論文目次 摘要 III
誌謝 VII
目錄 VIII
圖目錄 XI
表目錄 XVII
第一章 緒論 1
1.1 研究動機 1
1.2 目標與貢獻 3
1.3 論文架構簡介 4
第二章 Matlab/Simulink 模型化基礎設計 5
2.1 傳統設計方法及問題 5
2.2 模型化基礎設計方法 6
2.2.1 系統及演算法硬體模型開發 9
2.2.2 定點數轉換及驗證[30] 10
2.2.3 HDL硬體程式碼自動生成[34] 13
2.2.4 HDL硬體程式碼模擬驗證[41] 15
2.2.5 FPGA-in-the-Loop硬體驗證[42] 16
2.3 文獻研究探討 18
2.4 比較與討論 24
第三章 數位控制降壓型轉換器系統 27
3.1 架構及原理 27
3.2 功率級電路 31
3.3 類比-數位轉換器 33
3.4 數位控制器 34
3.4.1 數位編碼器 35
3.4.2 數位補償器 36
3.4.3 數位脈波寬度調變器 38
3.5 系統規格與Matlab/Simulink建模 41
3.5.1 規格及架構 41
3.5.2 功率級電路 43
3.5.3 類比-數位轉換器 45
3.5.4 數位控制器 47
第四章 使用模型化基礎快速設計降壓型轉換器之數位控制電路 58
4.1 傳統設計方法(人工撰寫數位控制器之HDL程式碼) 58
4.1.1 傳統數位控制降壓型轉換器之設計流程 58
4.1.2 本實驗室數位控制降壓型轉換器之設計流程 61
4.2 傳統設計方法模擬結果(本實驗室) 63
4.3 模型化基礎設計(自動生成數位控制器之HDL程式碼) 66
4.3.1 數位編碼器 66
4.3.2 數位補償器 69
4.3.3 數位脈波寬度調變器 71
4.4 模型化基礎設計模擬結果 72
4.4.1 數位控制器HDL程式碼模擬驗證 73
4.4.2 數位控制器FPGA-in-the-Loop硬體驗證 75
4.5 傳統V.S 模型化基礎設計結果比較 78
第五章 FPGA系統實作與量測驗證 80
5.1 實作平台與電路版設計 80
5.2 量測規劃與量測環境 82
5.3 量測結果 82
5.3.1 穩態量測 83
5.3.2 暫態量測 85
5.4 成果比較與討論 87
5.4.1 量測結果比較 87
5.4.2 FPGA使用資源比較 88
第六章 晶片實作與量測驗證 91
6.1 晶片電路佈局及整合 91
6.1.1 功率級 92
6.1.2 類比-數位轉換器 92
6.1.3 數位控制器電路 93
6.2 佈局後全晶片模擬結果 93
6.3 量測規劃與量測環境 95
6.4 量測結果 97
6.4.1 穩態量測 98
6.4.2 暫態量測 98
6.5 成果比較與討論 99
第七章 結論 101
7.1 總結與貢獻 101
7.2. 未來工作與研究方向 101
7.2.1 Matlab (.m) + Finite State Machine (Stateflow) 101
7.2.2 進階合成(High-Level Synthesis, HLS) 102
7.2.3 硬體在環測試(Hardware in the loop, HIL) 102
7.2.4 自動生成C程式碼 102
參考文獻 103
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