||Benchmarking the Impact of Variation in Hf0.5Zr0.5O2 based Ferroelectric FET on its Performance in Neuromorphic Computing
||MS Degree Program on Nano-Integrated Circuit Engineering
Recent advent in the research of hafnium oxide based ferroelectric materials have delineated its potential for being used as a steep slope device or as a memory device. Although, the science behind the origin of steep slope is a topic of utmost controversy among the scientific community, the non-volatile memory application is unanimously accepted. Higher immunity towards random telegraphic noise, flicker noise than resistive memory, higher endurance than the magnetic memory, higher bit density than the SRAM makes this an ideal candidate from next generation memory application.
Amidst all these advantages, the random ferroelectric and dielectric phase distribution caused variation and trapping-detrapping induced variation instigate high device to device variations in the ferroelectric field effect transistors. The pivotal point of this thesis is to analyze process and temperature induced variation in ferroelectric field effect transistors and investigate plausible remedies to mitigate or abate the effects of these variations.
We commenced our work by fabricating Hf0.5Zr0.5O2 based ferroelectric capacitors by depositing hafnium oxide and zirconium oxide in 1:1 ration by atomic layer deposition method with titanium nitride as top and bottom electrode. We have analyzed the random ferroelectric dielectric phase instigated variation in the fabricated capacitors and built a spice model based on modified Landau-Ginsburg free energy model. The model takes care of domain boundary energy to simulate the transition path in presence of multiple domains in ferroelectric capacitors.
Subsequently we extended our work to fathom the nanoscale variations in ferroelectric FETs by fabricating ferroelectric FinFET devices. Impact of trapping and phase variations have been investigated. We perceived that polycrystal structure of Hf0.5Zr0.5O2 engenders huge device to device variations in the threshold voltage of deeply scaled devices, with a strong gate length dependence on the variations.
Apart from the huge device to device variations, which can be effectively subsided by intelligent neural network architectures, we have obtained endurance up to 109 cycles, low cycle to cycle variations by increasing the fin numbers in the devices. We have also observed excellent long-term potentiation and depression characteristics for devices with gate length 50nm and width 20nm with a minimum write latency of 1μs within an operating temperature range of 233K to 358K.
List of Figure ix
List of Table x
Chapter 1. Introduction 1
1.1 Research motivation 1
1.2 Ferroelectricity and Its Origin 1
1.3 Ferroelectricity in Binary Oxides 3
1.4 Crystal structure 4
1.5 Advantage of HZO Over Perovskite Materials 5
Chapter 2. Fabrication and Characterization of HZO Based Ferroelectric (FE) Capacitors 6
2.1 Fabrication of FE Capacitors 6
2.2 Material Characterization of FE Capacitors 8
2.2.1 Atomic Force Microscopy (AFM) 8
2.2.2 Transmission Electron Microscopy (TEM) and Energy-dispersive X-ray Spectroscopy (EDS) Analysis 9
2.2.3 X-ray Diffraction Analysis (XRD) 10
2.3 Electrical Characterization of Ferroelectric Capacitor 12
2.3.1 Polarization – Voltage Curve 12
2.3.2 Capacitance – Voltage Curve 13
2.4 Simulation of Ferroelectric Capacitor 14
2.4.1 Landau-Khalatnikov Theory 14
2.4.2 Device Modeling 15
2.4.3 Simulation Result 17
Chapter 3. Fabrication and Characterization of HZO Based Ferroelectric FET 19
3.1 Process Flow of Ferroelectric FinFET 20
3.1.1 Fabrication of Fin and Active Region 21
3.1.2 Gate Stack Development 22
3.1.3 Ion Implantation and Diffusion 23
3.1.4 Passivation and Metallization 23
3.2 Material Analysis of Ferroelectric FET 24
3.3 Electrical Characterization of Ferroelectric FET 25
3.3.1 DC Characterization of Ferroelectric FET 26
3.3.2 Program and Erase Operations in Ferroelectric FET 27
3.3.3 Long Term Potentiation and Long Term Depression 31
Chapter 4. Analysis and Mitigation of Process and Trapping Induced Variation in Ferroelectric FET 35
4.1 Random Ferroelectric Phase Induced Variation 35
4.1.1 Mitigation of Random Phase Distribution Variation: 36
4.2 Trapping Induced Variation 38
4.2.1 Trapping 38
4.2.2 Effects of Trapping 39
4.2.3 Mitigation of Trapping Induced Variations 41
4.3 Temperature Induced Variation 44
4.3.1 Mitigation of Temperature Induced Variations 45
Chapter 5. Benchmarking the Perfromance of Ferroelectric FET 47
Chapter 6. Conclusion 48
Answer to Thesis Defense Question 50
 Z.-T. Lin and V. P.-H. Hu, "Reduced RTN Amplitude and Single Trap induced Variation for Ferroelectric FinFET by Substrate Doping Optimization," in Silicon Nanoelectronics Workshop (SNW), 2019.
 C.-I. Lin, A. I. Khan, S. Salahuddin and C. Hu, "Effects of the Variation of Ferroelectric Properties on Negative Capacitance FET Characteristics," IEEE Transactions on Electron Devices , vol. 63, no. 5, pp. 2197 - 2199, 2016.
 C. Kittel, Introduction to Solid State Physics, John Wiley, 2018.
 R. P. Feynman, "The Feynman Lectures Website," [Online]. Available: https://www.feynmanlectures.caltech.edu/info/.
 S. J. Kim, J. Mohan, S. R. Summerfelt and J. Kim, "Ferroelectric Hf0.5Zr0.5O2 Thin Films: A Review of Recent," in The Minerals, Metals & Materials Society (TMS), 2018.
 A. K. Saha, B. Grisafe, S. Datta and S. K. Gupta, "Microscopic Crystal Phase Inspired Modeling of Zr Concentration Effects in Concentration Effects in Hf1-xZrxO2 Thin Films," in VLSI, 2019.
 S. S. Cheema, D. Kwon, N. Shanker, R. d. Reis, S.-L. Hsu, J. Xiao, H. Zhang, R. Wagner, A. Datar, M. R. McCarter, C. R. Serrao, A. K. Yadav, G. Karbasian, C.-H. Hsu, A. J. Tan, L.-C. Wang, V. Thakare, X. Zhang, A. Mehta, E. Karapetrova, R. V. Chopdekar, P. Shafer, E. Arenholz, C. Hu, R. Proksch, R. Ramesh, J. Ciston and S. Salahuddin, "Enhanced ferroelectricity in ultrathin films grown directly on silicon," Nature, vol. 580, pp. 478-482, 22 April 2020.
 F. P. G. Fengler, M. Pešić, S. Starschich, T. Schneller, U. Böttger, T. Schenk, M. H. Park, T. Mikolajick and U. Schroeder, "Comparison of hafnia and PZT based ferroelectrics for future non-volatile FRAM applications," in European Solid-State Device Research Conference (ESSDERC), 2016.
 M. N. K. Alam, B. Kaczer, L.-Å. Ragnarsson, M. Popovici, G. Rzepa, N. Horiguchi, M. Heyns and J. V. Houdt, "On the Characterization and Separation of Trapping and Ferroelectric Behavior in HfZrO FET," Electron Devices Society (EDS), vol. 7, pp. 855 - 862, 2019.
 J. E. Jaffe, R. A. Bachorz and M. Gutowski, "Low-temperature polymorphs of ZrO2 and HfO2 : A density-functional theory study," vol. 37, no. 2, 2005.
 M. H. Lee, S. T. Fan, C. H. Tang, P. G. Chen, Y. C. Chou, H. H. Chen, J. Y. Kuo, M. J. Xie, S. N. Liu, M. H. Liao, C. A. Jong, K. S. Li, M. C. Chen and C. W. Liu, "Physical Thickness 1.x nm Ferroelectric HfZrOx Negative Capacitance FETs," in International Electron Devices Meeting (IEDM), 2016.
 S. De, M. A. Baig, B.-H. Qiu, D. Lu, P.-J. Sung, F. Hsueh, Y.-J. Lee and C.-J. Su, "Tri-Gate Ferroelectric FET Characterization and Modelling for Online Training of Neural Networks at Room Temperature and 233K," in Device Research Conference (DRC), 2020.
 C. Korok, "Design and Characterization of Ferroelectric Negative Capacitance," Berkeley, 2018.
 C.-W. Wang, H. Ku, C. Y. Chiu, S. De, B.-H. Qiu, C. Shin and D. Lu, "Compact model for PZT ferroelectric capacitors with voltage dependent switching behavior," Semiconductor Science and Technology (SST), vol. 35, no. 5, 2020.
 P.-J. Sung, C.-J. Su, S.-H. Lo, F.-K. Hsueh, D. D. Lu, Y.-J. Lee and T.-S. Chao, "Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter," Journal of the Electron Devices Society, vol. 8, pp. 474 - 480, 2020.
 V. P.-H. Hu, H.-H. Lin, Z.-A. Zheng, Z.-T. Lin, Y.-C. Lu, L.-Y. Ho, Y.-W. Lee, C.-W. Su and C.-J. Su, "Split-gate fefet (sg-fefet) with dynamic memory window modulation for non-volatile memory and neuromorphic applications," in Symposium on VLSI Technology, 2019.
 I. Yoon, M. Chang, K. Ni, M. Jerry, S. Gangopadhyay, G. Smith, T. Hamam, V. Narayanan, J. Romberg, S.-L. Lu, S. Datta and A. Raychowdhury, "A FeFET Based Processing-In-Memory Architecture for Solving Distributed Least-Square Optimizations," in Device Research Conference (DRC), 2018.
 G. Bersuker, J. H. Sim, C. S. Park, C. D. Young, S. V. Nadkarni, R. Choi and B. H. Lee, "Mechanism of electron trapping and characteristics of traps in HfO2 gate stacks," IEEE Transactions on Device and Materials Reliability, vol. 7, pp. 138-145, 2007.
 T. Ma and N. Gong, "Retention and endurance of fefet memory cells," in International Memory Workshop (IMW), 2019.
 T. Ali, P. Polakowski, S. Riedel, T. Büttner, T. Kämpfe, M. Rudolph, B. Pätzold, K. Seidel, D. Löhr, R. Hoffmann, M. Czernohorsky, K. Kühnel, P. Steinke, J. Calvo, K. Zimmermann and J. Müller, "High Endurance Ferroelectric Hafnium Oxide-Based FeFET Memory Without Retention Penalty," Transactions on Electron Devices (TED), vol. 65, no. 9, pp. 3769 - 3774, 2018.
 F. Winkler, M. Pešić, C. Richter, M. Hoffmann, T. Mikolajick and J. W. Bartha, "Demonstration and Endurance Improvement of p-channel Hafnia-based Ferroelectric Field Effect Transistors," in Device Research Conference (DRC), 2019.
 M. Jerry, P.-Y. Chen, J. Zhang, P. Sharma, K. Ni, S. Yu and S. Datta, "Ferroelectric FET analog synapse for acceleration of deep neural network training," in International Electron Devices Meeting (IEDM), 2017.
 S. De, B.-H. Qiu, M. A. Baig, D. D. Lu, P.-J. Sung, Y.-J. Lee and F.-K. Hsueh, "Impact of Noise and Device Variation in Nanoscale Ferroelectric FinFETs towards its," in VLSI, 2020.
 C. Oh, A. Tewari, K. Kim, U. S. Kumar, C. Shin, M. Ahn and S. Jeon, "Comprehensive study of high pressure annealing on the ferroelectric properties of Hf0.5Zr0.5O2 thin films," Nanotechnology, 2019.
 J. Frascaroli, F. G. Volpe, S. Brivio and S. Spiga, "Effect of Al doping on the retention behavior of HfO2 resistive switching memories," Microelectronic Engineering, pp. 104-104, 2015.
 W. Chung, M. Si and P. D. Ye, "First Demonstration of Ge Ferroelectric Nanowire FET as Synaptic Device for Online Learning in Neural Network with High Number of Conductance State and Gmax/Gmin," in International Electron Devices Meeting (IEDM), 2018.
 W. Xiao, C. Liu, Y. Peng, S. Zheng, Q. Feng, C. Zhang, J. Zhang, Y. Hao, M. Liao and Y. Zhou, "Memory Window and Endurance Improvement of Hf0.5Zr0.5O2-Based FeFETs with ZrO2 Seed Layers Characterized by Fast Voltage Pulse Measurements," Nanoscale Research Letters, no. 254, 2019.
 P.-Y. Chen, X. Peng and S. Yu, "NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures," in IEEE International Electron Devices Meeting (IEDM), 2017.
 S. H. Jo, T. Chang, I. Ebong, B. B. Bhadviya, P. Mazumder and W. Lu, "Nanoscale Memristor Device as Synapse in Neuromorphic Systems," Nano Lett., vol. 10, no. 4, pp. 1297-1301, 2010.
 L. Gao, I.-T. Wang, P.-Y. Chen, S. Vrudhula, J.-s. Seo, Y. Cao, T.-H. Hou and S. Yu, "Fully parallel write/read in resistive synaptic array for accelerating on-chip learning," Nanotechnology, vol. 26, 2015.
 S. Park, A. Sheri, J. Kim, J. Noh, J. Jang, M. Jeon, B. Lee, B. R. Lee, B. H. Lee and H. Hwang, "Neuromorphic speech systems using advanced ReRAM-based synapse," in International Electron Devices Meeting (IEDM), 2013.
 J. Woo, K. Moon, J. Song, S. Lee, M. Kwak, J. Park and H. Hwang, "Improved Synaptic Behavior Under Identical Pulses Using AlOx /HfO2 Bilayer RRAM Array for Neuromorphic Systems," Electron Device Letter (EDL), vol. 37, no. 8, pp. 994-997, 2016.
 D. Kuzum, R. G. D. Jeyasingh, B. Lee and H.-S. P. Wong, "Nanoelectronic Programmable Synapses Based on Phase Change Materials for Brain-Inspired Computing," Nano Lett., vol. 12, no. 2179-2186, 2012.
 A. I. Khan, "Negative capacitance for ultra-low power computing," Berkeley, 2015.
 M. Kobayashi, N. Ueyama, K. Jang and T. Hiramoto, "Experimental Study on Polarization-Limited Operation Speed of Negative Capacitance FET with Ferroelectric HfO2," in International Electron Devices Meeting, 2016.
 W. H. Lu, P.-C. Lin, T.-Y. Huang, C.-H. M.-J. Yang, I.-J. Huang and P. Lehnen, "The characteristics of hole trapping in HfO2/SiO2 gate dielectrics with Tin gate electrode," Applied Physics Letters, vol. 85, pp. 3525-3527, 2004.
 M. H. Park, Y. H. Lee and C. S. Hwang, "Understanding ferroelectric phase formation in doped HfO2 thin films based on classical nucleation theory," Nanoscale, vol. 11, p. 19477–19487, 2019.
 C.-I. Lin, A. I. Khan, S. Salahuddin and C. Hu, "Effects of the Variation of Ferroelectric Properties on Negative Capacitance FET Characteristics," IEEE Transactions on Electron Devices, vol. 63, no. 5, pp. 2197 - 2199, Volume: 63 , Issue: 5 , May 2016 ) 2016.