進階搜尋


下載電子全文  
系統識別號 U0026-1109201404491000
論文名稱(中文) 著重於節省寫入能耗的非揮發性靜態隨機存取記憶體設計
論文名稱(英文) Design of a Saving-Write-Energy Non-Volatile SRAM
校院名稱 成功大學
系所名稱(中) 電機工程學系
系所名稱(英) Department of Electrical Engineering
學年度 102
學期 2
出版年 103
研究生(中文) 鄒亦淞
研究生(英文) Yi-Sung Tsou
電子信箱 n26004993@mail.ncku.edu.tw
學號 N26004993
學位類別 碩士
語文別 英文
論文頁數 78頁
口試委員 口試委員-洪浩喬
口試委員-李順裕
口試委員-張順志
指導教授-邱瀝毅
中文關鍵字 非揮發性靜態隨機存取記憶體  冗餘位元寫入  電阻式記憶元件  常閉瞬開運算  能量擷取電子系統  快取記憶體 
英文關鍵字 nvSRAM  Redundant bit-write  RRAM device  Normally-off computing  Energy harvesting  Cache 
學科別分類
中文摘要 隨著先進製程的微縮,使得漏電流問題成為靜態隨機存取記憶體最重要的挑戰之一。傳統的做法通常會使用電源閘控或是將待機電源降低至資料保持電壓來降低待機能耗。隨著非揮發性靜態隨機存取記憶體的出現,解決了待機模式下漏電流的問題。其作法是在關閉電源之前先將資料備份至非揮發性記憶體中,接著在待機模式將電源關閉來消除待機能耗,以達到更進一步的節省能量。但並非所有的資料都是需要備份的。因此在本論文中,以電阻式記憶體元件為例,改良傳統的非揮發性靜態隨機存取記憶單元,提出一個具有考慮冗餘位元寫入的10T2R非揮發性靜態隨機存取記憶體,並搭配冗餘位元感知控制器。當靜態隨機存取記憶單元的資料與非揮發性記憶元件的資料相同時,不進行備份動作。只有在靜態隨機存取記憶單元的資料與非揮發性記憶元件的資料不同時,才進行備份動作。如此一來,將可省下備份時資料覆寫的能量消耗。模擬結果顯示,當高電阻態為10MΩ以上時,其能量節省可達93%以上。且當冗餘位元寫入機率為25%以上時候,可以節省能量。該技術可應用於常閉瞬開運算、能量擷取電子系統、以及L2或L3快取記憶體等。
英文摘要 With the advancement of technology scaling, the leakage current issue becomes one of the most important challenges for SRAMs. Existing approaches usually use power gating or low supply voltage well-known data retention voltage to reduce the leakage energy consumption in standby mode. With the advent of nvSRAM, leakage current can be fully eliminated. Compared with conventional approaches, it can reach further energy saving by using powering off its supply voltage when data-backup is performed. However, not all of data are needed to back up. In this thesis, we propose a novel 10T2R RRAM-based nvSRAM with redundant bit-writes-aware controller which is considering redundant bit-writes condition. If data stored in SRAM cells are the same as that in RRAM devices, backup can be skipped. Otherwise, backup is performed. As a result, backup energy for the data can be saved under redundant bit-writes conditions. Simulation shows that energy saving can reach by up to 93% when high resistive state is larger than 10MΩ. And as long as the probability of the redundant bit-writes is larger than 25% probability, the backup energy saving is achieved. The technique can be applied to normally-off computing systems, energy harvesting systems, L2/L3 Cache, and so on.
論文目次 Chapter 1 Introduction 1
1.1 Preliminary 1
1.2 Motivation 7
1.3 Contributions 10
1.4 Thesis Organization 11
Chapter 2 Conventional nvSRAMs 12
2.1 6T2R nvSRAM 12
2.2 8T2R nvSRAM 16
2.3 Rnv8T nvSRAM 17
2.4 7T2R nvSRAM 20
2.5 9T2R nvSRAM 21
2.6 Summary 23
Chapter 3 Analyses of nvSRAMs 25
3.1 Break-Even Time (BET) analysis 25
3.2 Balanced Time (BT) analysis 26
3.3 Static Noise Margin (SNM) analysis 28
3.4 Figure of Merit (FOM) analysis 30
Chapter 4 Proposed nvSRAM Design 31
4.1 Proposed 10T2R nvSRAM Cell Design 31
4.2 Redundant Bit-Writes-Aware Controller Design 34
4.3 Power switch design for STORE-SET operation 38
4.4 Operating Principle 41
Chapter 5 Experimental Results 57
5.1 Simulation Circuits and Environment 57
5.2 Comparison of STORE energy 58
5.3 Comparison of Balanced Time (BT) 59
5.4 Comparison of Static Noise Margin (SNM) 61
5.5 Comparison of nvSRAM cell layout 62
5.6 Comparison of Figure of Merit (FOM) 63
5.7 RRAM lifetime testing for nvCache 67
5.8 Layout and Chip Implementation 69
Chapter 6 Conclusion 72
Chapter 7 Future Works 73
References 74
參考文獻 [1] M. H. Abu-Rahma and M. Anis, Nanometer Variation-Tolerant SRAM. Springer, 2013.
[2] C.-Y. Chen, H.-C. Shih, C.-W. Wu, C.-H. Lin, P.-F. Chiu, S.-S. Sheu, and F. T. Chen, "RRAM Defect Modeling and Failure Analysis Based on March Test and a Novel Squeeze-Search Scheme," IEEE Trans. on Computers, vol. PP, pp. 1-1, 2014.
[3] C. Muller, D. Deleruyelle, and O. Ginez, Emerging Memory Concepts: Materials, Modeling and Design. Springer, 2011.
[4] M.-T. Chang, P. Rosenfeld, S.-L. Lu, and B. Jacob, "Technology Comparison for Large Last-Level Caches (L3Cs): Low-Leakage SRAM, Low Write-Energy STT-RAM, and Refresh-Optimized eDRAM," in Proc. IEEE 19th International Symposium on High Performance Computer Architecture (HPCA2013), 2013, pp. 143-154.
[5] M. Qazi, M. E. Sinangil, and A. P. Chandrakasan, "Challenges and Directions for Low-Voltage SRAM," IEEE Design & Test of Computers, vol. 28, pp. 32-43, 2011.
[6] A. Pavlov and M. Sachdev, CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies. Springer, 2008.
[7] T. Perez and C. A. F. D. Rose, "Non-Volatile Memory: Emerging Technologies And Their Impacts on Memory Systems," Technical Report, 2010.
[8] M. She, "Semiconductor Flash Memory Scaling," Ph. D, Engineering-Electrical Engineering and Computer Sciences, University of California, Berkeley, 2003.
[9] H.-S. P. Wong, S. Raoux, S. Kim, J. Liang, J. P. Reifenberg, B. Rajendran, M. Asheghi, and K. E. Goodson, "Phase Change Memory," Proceedings of the IEEE, vol. 98, pp. 2201-2227, 2010.
[10] K. R. Udayakumar, T. San, J. Rodriguez, S. Chevacharoenkul, D. Frystak, J. Rodriguez-Latorre, C. Zhou, M. Ball, P. Ndai, S. Madan, H. McAdams, S. Summerfelt, and T. Moise, "Low-Power Ferroelectric Random Access Memory Embedded in 180nm Analog Friendly CMOS Technology," in Proc. IEEE International Memory Workshop (IMW), 2013, pp. 128-131.
[11] X. Dong, N. P. Jouppi, and Y. Xie, "PCRAMsim: System-Level Performance, Energy, and Area Modeling for Phase-Change RAM," in Proc. International Conference on Computer-Aided Design (ICCAD), 2009, pp. 269-275.
[12] K. Johguchi, T. Egami, and K. Takeuchi, "Reliable, Low-Power Super-Lattice Phase-Change Memory without Melting and Write-Pulse Down Slope," in Proc. International Reliability Physics Symposium (IRPS), 2013, pp. MY.5.1-MY.5.4.
[13] Y. Fujisaki, "Review of Emerging New Solid-State Non-Volatile Memories," Japanese J. of Applied Physics, April 8 2013.
[14] H. Y. Cheng, J. Y. Wu, R. Cheek, S. Raoux, M. BrightSky, D. Garbin, S. Kim, T. H. Hsu, Y. Zhu, E. K. Lai, E. Joseph, A. Schrott, S. C. Lai, A. Ray, H. L. Lung, and C. Lam, "A thermally Robust Phase Change Memory by Engineering the Ge/N Concentration in (Ge, N)xSbyTez Phase Change Material," in Proc. International Electron Devices Meeting (IEDM), 2012, pp. 31.1.1-31.1.4.
[15] Y. Huai, "Spin-transfer torque MRAM (STT-MRAM): Challenges and prospects," AAPPS Bulletin, vol. 18, pp. 33-40, 2008.
[16] K.-W. Kwon, S. H. Choday, Y. Kim, and K. Roy, "AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, pp. 712-720, 2014.
[17] A. V. Khvalkovskiy, D. Apalkov, S. Watts, R. Chepulskii, R. S. Beach, A. Ong, X. Tang, A. Driskill-Smith, W. H. Butler, P. B. Visscher, D. Lottis, E. Chen, V. Nikitin, and M. Krounbi, "Erratum: Basic principles of STT-MRAM cell operation in memory arrays," J. of Physics D: Applied Physics, 2013.
[18] X. Xue, W. Jian, J. Yang, F. Xiao, G. Chen, S. Xu, Y. Xie, Y. Lin, R. Huang, Q. Zou, and J. Wu, "A 0.13 μm 8 Mb Logic-Based CuxSiyO ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction," IEEE J. of Solid-State Circuits, vol. 48, pp. 1315-1322, 2013.
[19] Y. Y. Chen, L. Goux, S. Clima, B. Govoreanu, S. Member, R. Degraeve, G. S. Kar, A. Fantini, G. Groeseneken, D. J. Wouters, and M. Jurczak, "Endurance/Retention Trade-off on HfO2/Metal Cap 1T1R Bipolar RRAM," IEEE Trans. on Electron Devices, vol. 60, pp. 1114-1121, 2013.
[20] S. Boyn, S. Girod, V. Garcia, S. Fusil, S. Xavier, C. Deranlot, H. Yamada, C. Carrétéro, E. Jacquet, A. B. M. Bibes, and J. Grollier, "High-performance ferroelectric memory based on fully patterned tunnel junctions," Applied Physics Letters, vol. 104, pp. 052909-052909-3, 2014.
[21] E. Small, S. M. Sadeghipour, L. Pileggi, and M. Asheghi, "Thermal Analyses of Confined Cell Design for Phase Change Random Access Memory (PCRAM)," in Proc. Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), 2008, pp. 1046-1054.
[22] T. Kawahara, "Challenges toward gigabit-scale spin-transfer torque random access memory and beyond for normally off, green information technology infrastructure (Invited)," J. of Applied Physics, vol. 109, pp. 07D325-07D325-6, 2011.
[23] X. A. Tran, B. Gao, J. F. Kang, Z. R. W. L. Wu1, Z. Fang, K. L. Pey, Y. C. Yeo, A. Y. Du, B. Y. Nguyen, M. F. Li, and H. Y. Yu, "High Performance Unipolar AlOy/HfOx/Ni based RRAM Compatible with Si Diodes for 3D Application," in Proc. Symposium on VLSI Technology (VLSIT), 2011, pp. 44-45.
[24] S.-S. Sheu, K.-H. Cheng, M.-F. Chang, P.-C. Chiang, W.-P. Lin, H.-Y. Lee, P.-S. Chen, Y.-S. Chen, T.-Y. Wu, F. T. Chen, K.-L. Su, M.-J. Kao, and M.-J. Tsai, "Fast-Write Resistive RAM (RRAM) for Embedded Applications," IEEE Design & Test of Computers, vol. 28, pp. 64-71, 2011.
[25] K.-C. Chang, T.-M. Tsai, T.-C. Chang, H.-H. Wu, J.-H. Chen, Y.-E. Syu, G.-W. Chang, T.-J. Chu, G.-R. Liu, Y.-T. Su, M.-C. Chen, J.-H. Pan, J.-Y. Chen, C.-W. Tung, H.-C. Huang, Y.-H. Tai, D.-S. Gan, and S. M. Sze, "Characteristics and Mechanisms of Silicon-Oxide-Based Resistance Random Access Memory," IEEE Electron Device Letters, vol. 34, pp. 399-401, 2013.
[26] L. Kai, Z. Kailiang, W. Fang, Z. Jinshi, and W. Jun, "Simulation Study of dimensional effect on Bipolar Resistive Random Access Memory (RRAM)," in Proc. International Nanoelectronics Conference (INEC), 2013, pp. 306-308.
[27] A. Chen, "Forming Voltage Scaling of Resistive Switching Memories," in Proc. Device Research Conference (DRC), 2013, pp. 181-182.
[28] P.-F. Chiu, M.-F. Chang, C.-W. Wu, and C.-H. Chuang, "Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications," IEEE J. of Solid-State Circuits, vol. 47, pp. 1483-1496, 2012.
[29] H. Y. Lee, P. S. Chen, T. Y. Wu, Y. S. Chen, C. C. Wang, P. J. Tzeng, C. H. Lin, F. Chen, and C. H. L. M.-J. Tsai, "Low Power and High Speed Bipolar Switching with A Thin Reactive Ti Buffer Layer in Robust HfO2 Based RRAM," in Proc. International Electron Devices Meeting (IEDM), 2008, pp. 1-4.
[30] P. Zhou, B. Zhao, J. Yang, and Y. Zhang, "Energy Reduction for STT-RAM Using Early Write Termination," in Proc. International Conference on Computer-Aided Design (ICCAD), 2009, pp. 264-268.
[31] K.-W. Kwon, S. H. Choday, Y. Kim, and K. Roy, "AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, pp. 712-720, 2014.
[32] O. Turkyilmaz, S. Onkaraiah, M. Reyboz, F. Clermidy, H. C. Anghel, J.-M. Portal, and M. Bocquet, "RRAM-based FPGA for “Normally Off, Instantly On” Applications," in Proc. International Symposium on Nanoscale Architectures (NANOARCH), 2012, pp. 101-108.
[33] W. Wang, A. Gibby, Z. Wang, T. W. Chen, S. Fujita, P. Griffin, Y. Nishi, and S. Wong, "Nonvolatile SRAM Cell," in Proc. International Electron Devices Meeting (IEDM), 2006, pp. 1-4.
[34] S.-S. Sheu, C.-C. Kuo, M.-F. Chang, P.-L. Tseng, L. Chih-Sheng, M.-C. Wang, C.-H. Lin, W.-P. Lin, T.-K. Chien, S.-H. Lee, S.-C. Liu, H.-Y. Lee, P.-S. Chen, Y.-S. Chen, C.-C. Hsu, F. T. Chen, K.-L. Su, T.-K. K. M.-J. Tsai, and M.-J. Kao, "A ReRAM Integrated 7T2R Non-volatile SRAM for Normally-off Computing Application," in Proc. IEEE Asian Solid-State Circuits Conference (A-SSCC), 2013, pp. 245-248.
[35] X. Xue, W. Jian, Y. Xie, Q. Dong, R. Yuan, and Y. Lin, "Novel RRAM Programming Technology for Instant-on and High-security FPGAs," in Proc. International Conference on ASIC (ASICON), 2011, pp. 291-294.
[36] K. Usami, Y. Goto, K. Matsunaga, S. Koyama, D. Ikebuchi, H. Amano, and H. Nakamura, "On-chip Detection Methodology for Break-Even Time of Power Gated Function Units," in Proc. International Symposium on Low Power Electronics and Design (ISLPED), 2011, pp. 241-246.
[37] Y. Shuto, S. Yamamoto, and S. Sugahara, "Static Noise Margin and Power-Gating Efficiency of a New Nonvolatile SRAM Cell Based on Pseudo-Spin-Transistor Architecture," in Proc. IEEE International Memory Workshop (IMW), 2012, pp. 1-4.
[38] R. Wang, W. Zhang, T. Li, and D. Qian, "Leveraging Non-Volatile Storage to Achieve Versatile Cache Optimizations," Computer Architecture Letters, vol. PP, pp. 1-1, 2014.
[39] Y. Shuto, S. Yamamoto, and S. Sugahara, "Static noise margin and power-gating efficiency of a new nonvolatile SRAM cell based on pseudo-spintransistor architecture," in Proc. IEEE International Memory Workshop (IMW), 2012, pp. 1-4.
[40] H.Yoda, S.Fujita, N.Shimomura, E.Kitagawa, K.Abe, K.Nomura, H.Noguchi, and J.Ito, "Progress of STT-MRAM Technology and the Effect on Normally-off Computing Systems " in Proc. IEEE International Electron Devices Meeting (IEDM), 2012, pp. 11.3.1-11.3.4.
[41] ITRI. MRAM Device and Process Technology [Online]. Available: https://www.itri.org.tw/chi/tech-transfer/04.asp?RootNodeId=040&NodeId=041&id=2656
[42] CACTI [Online]. Available: http://quid.hpl.hp.com:9081/cacti/index.y?new
[43] K. Chen, J. Han, and F. Lombardi, "On the Nonvolatile Performance of Flip-Flop/SRAM Cells With a Single MTJ," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. PP, pp. 1-1, 2014.
論文全文使用權限
  • 同意授權校內瀏覽/列印電子全文服務,於2019-09-12起公開。
  • 同意授權校外瀏覽/列印電子全文服務,於2019-09-12起公開。


  • 如您有疑問,請聯絡圖書館
    聯絡電話:(06)2757575#65773
    聯絡E-mail:etds@email.ncku.edu.tw