||An Iterative Approach for Leakage Power and Rush Current Minimization using Power Gate Sizing and Wake-up Scheduling
||Department of Electrical Engineering
Electronic Design Automation
隨著製程技術的進步，單一晶片可容納的電晶體數目增加，導致系統中的漏電流功耗日益嚴重。如何解決其產生的漏電流功耗 (leakage power) 已經成為低功率晶片設計上一個重要的課題。Power Gating是一種廣泛用來降低漏電流功耗的技術。Power Gating由睡眠電晶體構成，睡眠電晶體的尺寸會影響系統的效能及漏電流功耗；系統電源被打開時，休眠電晶體的尺寸及開啟的順序會影響喚醒電流(rush current)的大小。本論文運用疊代的方法，結合電晶體尺寸規劃與喚醒排序，找出最小的電源閘電晶體尺寸及最佳的喚醒排程，確保Power Gating在各操作模式下都能保持低功率，與文獻比較，平均減少37%的電源閘控電晶體尺寸及減少37%的漏電流功耗；與文獻比較，降低25%的喚醒電流，由此證明本論文所提出的演算法的有效性。
With the advancement of semiconductor technology, single chip can accommodate the increased number of transistors, resulting in significant increase in system leakage power. Power gating is a widely used technique to reduce the leakage power consumption. Power gating contains a transistor, known as sleep transistor, whose size will affect the system performance and leakage power consumption. When the circuit is powered on, the rush current depends on turned on sleep transistor size and wake-up sequence. We propose an iterative approach combining sleep transistor sizing and wake-up scheduling to reduce the size of power gates and power-on rush current simultaneously. When compared to , the proposed approach decreases 37% in power gating transistor size and 37% in leakage power on average. It also decreases 25% on average in rush current compared with .
Chapter I Introduction 1
I.1 Motivation 1
I.1.1 System Power Consumption 2
I.1.2 Leakage Power Reduction 3
I.1.3 Rush Current Reduction 4
I.2 Overview of Thesis 5
I.3 Contributions 6
I.4 Thesis Organization 6
Chapter II Background 7
II.1 Power Gating 7
II.1.1 Power Gating Architecture 7
II.1.2 Power Gating Behavior 8
II.1.3 Power Gating Design Considerations 9
II.2 Power Gating Type 12
II.2.1 Power Gating Design Considerations 12
II.2.2 Coarse-Grain Power Gating (CPG) 13
II.2.3 Discussion about FPG and CPG 14
II.3 Coarse-Grain Power Gating 14
II.3.1 Multi-Vt Approach 14
II.3.2 Boosted-Gated Approach 16
II.3.3 Body-Bias Approach 18
II.3.4 Sizing Approach 22
Chapter III Related Works 24
III.1 Module-Based Structure Design (MBSD) 24
III.2 Cluster-Based Structure (CBSD) 25
III.3 Distributed Sleep Transistor Network (DSTN) 28
III.4 Considering Charge Balance of DSTN (CCB) 30
III.5 Considering Temporal Correlation of DSTN 32
III.6 Stepwise Wake-up Switching (SWS) 35
III.7 Fixed-Length Delay Chain (FLDC) 36
III.8 Two-Stage Power-On Daisy Chain (2SDC) 37
III.9 Estimation of Rush Current (EST) 38
III.10 Efficient Wake-up Strategy (EWS) 40
Chapter IV Voltage Balance and Intelligent Scheduling Algorithm 45
IV.1 Problem Definition 45
IV.2 Proposed Flow 47
IV.2.1 Waveform Collection 48
IV.2.2 Model Construction 51
IV.2.3 Initialize RST 52
IV.2.4 Voltage Drop Simulation 53
IV.2.5 Record Max Slack 54
IV.2.6 Resizing Sleep Transistor 54
IV.2.7 Reconfigure MIC 57
IV.2.8 Wake-up Scheduling 58
IV.2.9 Wake-up Simulation 60
IV.2.10 Record Time Slack 60
IV.2.11 Refined Sizing 61
IV.3 Summary 66
Chapter V Experimental Results 69
V.1 Experimental Setup 69
V.1.1 Calculation 69
V.1.2 Experimental Procedure 70
V.1.3 Test Circuit Information 74
V.2 Experimental Results 75
Chapter VI Conclusion and Future Work 87
VI.1 Conclusion 87
VI.2 Future Work 88
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