
系統識別號 
U00261009201322493100 
論文名稱(中文) 
針對漏電流功耗及浪湧電流最小化運用電源閘電晶體尺寸規劃及喚醒排程之疊代法 
論文名稱(英文) 
An Iterative Approach for Leakage Power and Rush Current Minimization using Power Gate Sizing and Wakeup Scheduling 
校院名稱 
成功大學 
系所名稱(中) 
電機工程學系碩博士班 
系所名稱(英) 
Department of Electrical Engineering 
學年度 
101 
學期 
2 
出版年 
102 
研究生(中文) 
李宗儒 
研究生(英文) 
ZongRu Lee 
學號 
n26991611 
學位類別 
碩士 
語文別 
英文 
論文頁數 
94頁 
口試委員 
指導教授邱瀝毅 口試委員張順志 口試委員林家民 口試委員黃俊銘

中文關鍵字 
電源閘
電子設計自動化

英文關鍵字 
Power gate
Electronic Design Automation

學科別分類 

中文摘要 
隨著製程技術的進步，單一晶片可容納的電晶體數目增加，導致系統中的漏電流功耗日益嚴重。如何解決其產生的漏電流功耗 (leakage power) 已經成為低功率晶片設計上一個重要的課題。Power Gating是一種廣泛用來降低漏電流功耗的技術。Power Gating由睡眠電晶體構成，睡眠電晶體的尺寸會影響系統的效能及漏電流功耗；系統電源被打開時，休眠電晶體的尺寸及開啟的順序會影響喚醒電流(rush current)的大小。本論文運用疊代的方法，結合電晶體尺寸規劃與喚醒排序，找出最小的電源閘電晶體尺寸及最佳的喚醒排程，確保Power Gating在各操作模式下都能保持低功率，與文獻[28]比較，平均減少37%的電源閘控電晶體尺寸及減少37%的漏電流功耗；與文獻[31]比較，降低25%的喚醒電流，由此證明本論文所提出的演算法的有效性。

英文摘要 
With the advancement of semiconductor technology, single chip can accommodate the increased number of transistors, resulting in significant increase in system leakage power. Power gating is a widely used technique to reduce the leakage power consumption. Power gating contains a transistor, known as sleep transistor, whose size will affect the system performance and leakage power consumption. When the circuit is powered on, the rush current depends on turned on sleep transistor size and wakeup sequence. We propose an iterative approach combining sleep transistor sizing and wakeup scheduling to reduce the size of power gates and poweron rush current simultaneously. When compared to [28], the proposed approach decreases 37% in power gating transistor size and 37% in leakage power on average. It also decreases 25% on average in rush current compared with [31].

論文目次 
Chapter I Introduction 1
I.1 Motivation 1
I.1.1 System Power Consumption 2
I.1.2 Leakage Power Reduction 3
I.1.3 Rush Current Reduction 4
I.2 Overview of Thesis 5
I.3 Contributions 6
I.4 Thesis Organization 6
Chapter II Background 7
II.1 Power Gating 7
II.1.1 Power Gating Architecture 7
II.1.2 Power Gating Behavior 8
II.1.3 Power Gating Design Considerations 9
II.2 Power Gating Type 12
II.2.1 Power Gating Design Considerations 12
II.2.2 CoarseGrain Power Gating (CPG) 13
II.2.3 Discussion about FPG and CPG 14
II.3 CoarseGrain Power Gating 14
II.3.1 MultiVt Approach 14
II.3.2 BoostedGated Approach 16
II.3.3 BodyBias Approach 18
II.3.4 Sizing Approach 22
Chapter III Related Works 24
III.1 ModuleBased Structure Design (MBSD) 24
III.2 ClusterBased Structure (CBSD) 25
III.3 Distributed Sleep Transistor Network (DSTN) 28
III.4 Considering Charge Balance of DSTN (CCB) 30
III.5 Considering Temporal Correlation of DSTN 32
III.6 Stepwise Wakeup Switching (SWS) 35
III.7 FixedLength Delay Chain (FLDC) 36
III.8 TwoStage PowerOn Daisy Chain (2SDC) 37
III.9 Estimation of Rush Current (EST) 38
III.10 Efficient Wakeup Strategy (EWS) 40
Chapter IV Voltage Balance and Intelligent Scheduling Algorithm 45
IV.1 Problem Definition 45
IV.2 Proposed Flow 47
IV.2.1 Waveform Collection 48
IV.2.2 Model Construction 51
IV.2.3 Initialize RST 52
IV.2.4 Voltage Drop Simulation 53
IV.2.5 Record Max Slack 54
IV.2.6 Resizing Sleep Transistor 54
IV.2.7 Reconfigure MIC 57
IV.2.8 Wakeup Scheduling 58
IV.2.9 Wakeup Simulation 60
IV.2.10 Record Time Slack 60
IV.2.11 Refined Sizing 61
IV.3 Summary 66
Chapter V Experimental Results 69
V.1 Experimental Setup 69
V.1.1 Calculation 69
V.1.2 Experimental Procedure 70
V.1.3 Test Circuit Information 74
V.2 Experimental Results 75
Chapter VI Conclusion and Future Work 87
VI.1 Conclusion 87
VI.2 Future Work 88
References 89

參考文獻 
[1] N. S. Kim, T. Austin, D. Baauw, T. Mudge, K. Flautner, J. S. Hu, M. J. Irwin, M. Kandemir, and V. Narayanan, "Leakage current: Moore's law meets static power," Computer, vol. 36, no. 12, pp. 6875, 2003.
[2] R. R. Rao, A. Devgan, D. Blaauw, and D. Sylvester, "Parametric yield estimation considering leakage variability," in Proc. IEEE/ACM Design Automation Conference (DAC), 2004, pp. 442447.
[3] H. Chang and S. S. Sapatnekar, "Fullchip analysis of leakage power under process variations, including spatial correlations," in Proc. IEEE/ACM Design Automation Conference (DAC), 2005, pp. 523528.
[4] N. S. Kim, D. Blaauw, and T. Mudge, "Quantitative analysis and optimization techniques for onchip cache leakage power," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 13, no. 10, pp. 11471156, 2005.
[5] B. H. Calhoun, F. A. Honore, and A. P. Chandrakasan, "A leakage reduction methodology for distributed MTCMOS," IEEE J. SolidState Circuits (JSSC), vol. 39, no. 5, pp. 818826, 2004.
[6] Z. Liu and V. Kursun, "Charge Recycling MTCMOS for Low Energy Active/Sleep Mode Transitions," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2007, pp. 13891392.
[7] M. Keating, D. Flynn, R. Aitken, and K. Shi, Low power methodology manual: for systemonchip design: Springer, 2007.
[8] S. Kaijian and D. Howard, "Challenges in sleep transistor design and implementation in lowpower designs," in Proc. IEEE/ACM Design Automation Conference (DAC), 2006, pp. 113116.
[9] K. Shi and D. Howard, "Sleep Transistor Design and Implementation  Simple Concepts Yet Challenges To Be Optimum," in Proc. IEEE Int. Symp. on VLSI Design, Automation and Test (VLSIDAT), 2006, pp. 14.
[10] B. Kapoor, S. Hemmady, S. Verma, K. Roy, and M. A. D'Abreu, "Impact of SoC power management techniques on verification and testing," in Proc. Int. Symp. Quality Electronic Design (ISQED), 2009, pp. 692695.
[11] S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, "1V power supply highspeed digital circuit technology with multithresholdvoltage CMOS," IEEE J. SolidState Circuits (JSSC), vol. 30, no. 8, pp. 847854, 1995
[12] S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada, "A 1V highspeed MTCMOS circuit scheme for powerdown application circuits," IEEE J. SolidState Circuits (JSSC), vol. 32, no. 6, pp. 861869, 1997.
[13] S. Idgunji, "Case study of a low power MTCMOS based ARM926 SoC : Design, analysis and test challenges," in Proc. IEEE Int. Test Conference (ITC), 2007, pp. 110.
[14] H. Kawaguchi, K. I. Nose, and T. Sakurai, "A CMOS scheme for 0.5 V supply voltage with picoampere standby current," in Proc. IEEE Int. SolidState Circuits Conference (ISSCC), 1998, pp. 192193, 436.
[15] T. Inukai, M. Takamiya, K. Nose, H. Kawaguchi, T. Hiramoto, and T. Sakurai, "Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakagefree gigascale integration," in Proc. IEEE Custom Integrated Circuits Conference (CICC), 2000, pp. 409412.
[16] C. Y. Chang, W. B. Yang, C. J. Huang, and C. H. Chien, "New Power Gating Structure with Low Voltage Fluctuations by Bulk Controller in Transition Mode," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2007, pp. 37403743.
[17] J. Le Coz, P. Flatresse, S. Engels, A. Valentian, M. Belleville, C. Raynaud, D. Croain, and P. Urard, "Comparison of 65nm LP bulk and LP PDSOI with adaptive power gate body bias for an LDPC codec," in Proc. IEEE Int. SolidState Circuits Conference (ISSCC), 2011, pp. 336337.
[18] J. W. Tschanz, S. G. Narendra, Y. Ye, B. A. Bloechel, S. Borkar, and V. De, "Dynamic sleep transistor and body bias for active leakage power control of microprocessors," IEEE J. SolidState Circuits (JSSC), vol. 38, no. 11, pp. 18381845, 2003.
[19] J. Kao, S. Narendra, and A. Chandrakasan, "MTCMOS hierarchical sizing based on mutual exclusive discharge patterns," in Proc. IEEE/ACM Design Automation Conference (DAC), 1998, pp. 495500.
[20] S. Mutoh, S. Shigematsu, Y. Matsuya, H. Fukuda, T. Kaneko, and J. Yamada, "A 1V multithresholdvoltage CMOS digital signal processor for mobile phone application," IEEE J. SolidState Circuits (JSSC), vol. 31, no. 11, pp. 17951802, 1996.
[21] M. Anis, S. Areibi, M. Mahmoud, and M. Elmasry, "Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique," in Proc. IEEE/ACM Design Automation Conference (DAC), 2002, pp. 480485.
[22] M. Anis, S. Areibi, and M. Elmasry, "Design and optimization of multithreshold CMOS (MTCMOS) circuits," IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, vol. 22, no. 10, pp. 13241342, 2003.
[23] W. Wang, M. Anis, and S. Areibi, "Fast techniques for standby leakage reduction in MTCMOS circuits," in Proc. IEEE Int. SOC Conference (SOCC), 2004, pp. 2124.
[24] C. Long and L. He, "Distributed sleep transistor network for power reduction," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 12, no. 9, pp. 937946, 2004.
[25] E. Pakbaznia and M. Pedram, "CoarseGrain MTCMOS Sleep Transistor Sizing Using Delay Budgeting," in Proc. Design, Automation and Test in Europe (DATE), 2008, pp. 385390.
[26] D. S. Chiou, S. H. Chen, and S. C. Chang, "Sleep Transistor Sizing for Leakage Power Minimization Considering Charge Balancing," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 17, no. 9, pp. 13301334, 2009.
[27] D. S. Chiou, S. H. Chen, S. C. Chang, and C. W. Yeh, "Timing driven power gating," in Proc. IEEE/ACM Design Automation Conference (DAC), 2006, pp. 121124.
[28] D. S. Chiou, Y. T. Chen, D. C. Juan, and S. C. Chang, "Sleep Transistor Sizing for Leakage Power Minimization Considering Temporal Correlation," IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, vol. 29, no. 8, pp. 12851289, 2010.
[29] D. S. Chiou, D. C. Juan, Y. T. Chen, and S. C. Chang, "FineGrained Sleep Transistor Sizing Algorithm for Leakage Power Minimization," in Proc. IEEE/ACM Design Automation Conference (DAC), 2007, pp. 8186.
[30] YepChung Phong "A Fast and Effective Power Gating Transistor Sizing Algorithm for Leakage Power Minimization," in Department of Electrical Engineering Thesis for Master of Science, National ChengKung University, Tainan, Taiwan, January 2012.
[31] Suhwan Kim, Stephen V. Kosonocky, and Daniel R. Knebel, "Understanding and Minimizing Ground Bounce During Mode Transition of Power Gating Structures," in Proc. IEEE/ACM Int. Symp. Low Power Electronics and Design (ISLPED), 2003, pp. 22, 2527.
[32] Rahul Singh, JongKwan Woo, Hyunjoong Lee, So Young Kim, and Suhwan Kim "PowerGating Noise Minimization by ThreeStep WakeUp Partitioning, " IEEE Trans. Circuit and Syst.I, vol. 59, no. 4, April 2012.
[33] Seungwhun Paik, Sangmin Kim, and Youngsoo Shin, "Wakeup Synthesis and Its Buffered Tree Construction for Power Gating Circuit Designs," in Proc. IEEE/ACM Int. Symp. Low Power Electronics and Design (ISLPED), 2010, pp.413418
[34] YuTing Chen, DaCheng Juan, MingChao Lee, and ShihChieh Chang, "An Efficient Wakeup Schedule during Power Mode Transition Considering Spurious Glitches Phenomenon," in Proc. Int. Conf. ComputerAided Design (ICCAD), Nov. 2007, pp.779782.
[35] MingChao Lee, ShihChieh Chang, ChunSung Su, and Evan Tsai, "Performance and WakeUp Schedule Optimization of Power Gating Design," in Proc. Int. Conf. SoC Design (ISOCC), Nov. 2008, pp3639.
[36] DaCheng Juan, YuTing Chen, MingChao, and ShihChieh Chang, "An Efficient WakeUp Strategy Considering Spurious Glitches Phenomenon for Power Gating Design," IEEE Trans. Very Large Scale Integration Systems (VLSI), vol. 18, no. 2, pp.246255.
[37] J. M. Rabaey, Digital integrated circuits: a design perspective: Prentice Hall, 1996.
[38] B. Razavi, Design of analog CMOS integrated circuits: McGrawHill, 2001.
[39] T. Sakurai and A. R. Newton, "Alphapower law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE J. SolidState Circuits (JSSC), vol. 25, no. 2, pp. 584594, 1990.
[40] C. Prasad, M. Agostinelli, C. Auth, M. Brazier, R. Chau, G. Dewey, T. Ghani, M. Hattendorf, J. Hicks, J. Jopling, J. Kavalieros, R. Kotlyar, M. Kuhn, K. Kuhn, J. Maiz, B. McIntyre, M. Metz, K. Mistry, S. Pae, W. Rachmady, S. Ramey, A. Roskowski, J. Sandford, C. Thomas, C. Wiegand, and J. Wiedemer, "Dielectric breakdown in a 45 nm highk/metal gate process technology," in Proc. IEEE Int. Reliability Physics Symposium (IRPS), 2008, pp. 667668.
[41] Synopsys. SMICSynopsys Reference Flow 4.0. [Online]. Available: http://www.smics.com/eng/design/reference_flows07.php
[42] Synopsys and E. Wang. Synopsys Powergating Design Methodology based on SMIC 90nm Process. [Online]. Available:
http://www.synopsys.com.cn/information/snug/20072008collection/synopsyspowergatingdesignmethodologybasedonsmic90nmprocess
[43] T. Tanzawa and T. Tanaka, "A dynamic analysis of the Dickson charge pump circuit," IEEE J. SolidState Circuits (JSSC), vol. 32, no. 8, pp. 12311240, 1997.
[44] F. Assaderaghi, S. Parke, D. Sinitsky, J. Bokor, P. K. Ko, and H. Chenming, "A dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation," IEEE Electron Device Letters (EDL), vol. 15, no. 12, pp. 510512, 1994.
[45] K. Shimomura, H. Shimano, N. Sakashita, F. Okuda, T. Oashi, Y. Yamaguchi, T. Eimori, M. Inuishi, K. Arimoto, S. Maegawa, Y. Inoue, S. Komori, and K. Kyuma, "A 1V 46ns 16Mb SOIDRAM with body control technique," IEEE J. SolidState Circuits (JSSC), vol. 32, no. 11, pp. 17121720, 1997.
[46] H. Mostafa, M. Anis, and M. Elmasry, "A Novel Low Area Overhead Direct Adaptive Body Bias (DABB) Circuit for DietoDie and WithinDie Variations Compensation," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 19, no. 10, pp. 18481860, 2011.
[47] M. Barnasconi, "Systemc ams extensions: Solving the need for speed," in Proc. DAC Knowledge center, 2010.
[48] ISCAS Benchmarks. [Online]. Available:
http://www.pld.ttu.ee/~maksim/benchmarks/
[49] M. L. Bushnell, V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and MixedSignal VLSI Circuits, Lucent Technologies and Michael L. Bushnell, 2000

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