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系統識別號 U0026-1002201920071300
論文名稱(中文) 基於對數似然比之低複雜度接續消去名單極碼解碼器
論文名稱(英文) Low Complexity LLR-Based Successive-Cancellation List Decoder for Polar Codes
校院名稱 成功大學
系所名稱(中) 電機工程學系
系所名稱(英) Department of Electrical Engineering
學年度 107
學期 1
出版年 108
研究生(中文) 林榮德
研究生(英文) Long-De Lin
學號 N26044799
學位類別 碩士
語文別 英文
論文頁數 54頁
口試委員 指導教授-謝明得
口試委員-雷曉方
口試委員-郭致宏
口試委員-張雲南
中文關鍵字 極碼  接續消去  名單解碼  對數似然比  凍結位置樣式  比率-0/比率-1碼  重複碼  近似最大似然 
英文關鍵字 Polar codes  Successive cancellation  List decoding  Log-likelihood-ratio  Frozen-location patterns  Rate-0/Rate-1 codes  Repetition codes  Approximate maximum likelihood 
學科別分類
中文摘要 極碼 (polar codes) 因其可被證明用於實現通道容量而被視為編碼理論的最新突破,在現有的解碼方案中,接續消去名單 (successive-cancellation list, SCL) 解碼是主要的作法,可用來得到最佳的糾錯能力。然而,傳統的SCL解碼器在硬體實現上需要較大面積且其吞吐量過低,而後續相關研究並沒有同時對這兩種指標進行優化。本論文基於對數似然比 (log-likelihood-ratio, LLR) 的SCL解碼演算法與符號判斷,提出一種高重複使用的LLR記憶體以及簡化的部分總和產生器 (partial-sum generator, PSG) 來減小面積。另一方面,我們採用比率-0碼和重複碼的新凍結位置樣式 (frozen-location patterns) 來減少近似最大似然 (approximate maximum likelihood, AML) 解碼的排序階層,並進一步修改比率-0碼和比率-1碼來減少解碼週期。實驗結果顯示,基於本論文所提出之演算法而開發出的SCL解碼器,於名單大小為2的條件下,其所實現之4位元 (1024,512) 極碼解碼器設計的硬體效率可至少優於現有相關解碼器的 1.22倍。
英文摘要 Polar codes are the latest breakthrough in coding theory, as they can provably achieve the channel capacity. Among existing decoding schemes, successive-cancellation list (SCL) decoding is recognized as the main approach that can be applied to achieve the best error-correction performance. However, hardware implementation of the conventional SCL decoder usually consumes a large area and can only achieve low throughput. Recent research works were mainly focused on either reducing the hardware requirement or improving the resulting throughput. According to the log-likelihood-ratio (LLR) based SCL decoding algorithm and the concept of symbol decision, this thesis presents a highly reusable LLR memory structure and simplifies the partial-sum generator to reduce the overall area requirement of polar decoders. In addition, new frozen-location patterns of rate-0 and repetition codes were employed to decrease the number of sorting stages for approximate maximum likelihood decoding, and modified rate-0 and rate-1 codes were used to further reduce the decoding cycles. Experimental results reveal that the SCL decoder designed using the proposed algorithm and optimization schemes for a 4-bit (1024, 512) polar code with a list size of 2 can achieve at least 1.22 times the hardware efficiency of related works.
論文目次 摘   要 i
ABSTRACT ii
致謝 iv
Content v
List of Tables viii
List of Figures ix
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis organization 2
Chapter 2 Background 3
2.1 Channel polarization 3
2.2 Construction of polar codes 4
2.2.1 Channel combining 4
2.2.2 Channel splitting 5
2.2.3 Recursive channel transformations 5
2.2.4 Bit-reversed indexing 6
2.3 Successive-cancellation decoding 7
2.4 Architecture of SC decoder 8
2.4.1 Fully-parallel architecture 8
2.4.2 Tree architecture 9
2.4.3 Line architecture 10
2.4.4 Semi-parallel architecture 11
2.5 Simplified SC decoder 12
2.5.1 Min-sum approximation 12
2.5.2 Merged processing element and symbol-decision 13
2.5.3 Rate-0 and rate-1 nodes 14
2.6 Successive-cancellation list decoding 15
2.7 Architecture of semi-parallel SCL decoder 16
2.7.1 Metric computation unit 17
2.7.2 Zero-forcing unit and Frozen-location patterns 18
2.7.3 Sorter 19
2.7.4 Approximate maximum likelihood decoding 19
2.8 Quantization 22
Chapter 3 Proposed LLR-based SCL Decoder 23
3.1 Proposed SCL decoding for (1024, 512) polar codes 23
3.1.1 Architecture of 4-bit LLR-based SCL decoder with L=2 23
3.1.2 SCL decoding algorithm 25
3.2 Processing element unit 27
3.2.1 The simplification of g function 27
3.2.2 Non-uniform quantizer for LLR memory bank 29
3.3 LLR memory bank and multiplexer 30
3.3.1 Additional processing element unit without multiplexer connection 31
3.3.2 An efficient method for LLR memory bank with high usage rate 31
3.4 Metric computation unit, Frozen-location patterns and Sorter 33
3.4.1 Simplification on sorting 34
3.4.2 Fast sorting with additional judgement on Frozen-location patterns 35
3.5 Partial sum generator 37
3.6 Candidate memory bank 39
3.7 Encoder with Rate-1 node implementation 39
Chapter 4 Experimental Results 42
4.1 Analysis and comparison of simulation results 42
4.1.1 Quantization of different bit size on channel LLRs 42
4.1.2 Non-Uniform Quantization of SCL decoder 44
4.2 Estimation of SCL decoder with L=2 and k=2 45
4.3 Analysis and comparison of hardware performance 46
Chapter 5 Conclusion and Future Work 49
5.1 Conclusion 49
5.2 Future work 50
References 51
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