||An Investigation of Electron Transport in Zinc-Tin oxide Thin Film Transistor and its Application to Charge-Trapping Memory
||Department of Materials Science and Engineering
Charge trapping memory
Thin film transistors
本研究論文以溶液法製備氧化鋅錫(zinc-tin oxide ; ZTO)作為主動層之薄膜電晶體(thin film transistor ; TFT)，分別探討超薄主動層內部的微觀電子傳導機制以及閘極漏電流(gate-leakage current)發生的成因；最後，將元件製作成薄膜電晶體型電荷擷取式記憶體(TFT charge trapping memory)，並研究寫入與抹除特性。全文分為三大部分:
主題一探討閘極漏電流通過結構為p+-Si(閘極)/SiO2(介電層)/ZTO(主動層)/Al(源極/汲極)的底部閘極式TFT的傳輸機制。結果發現當主動層與介電層的面積比大於27 %時，電子可以通過100 nm厚的SiO2介電層形成閘極漏電流；相對的，當面積比小於1 %時，閘極漏電流便可以有效的降低。造成漏電流發生的主因是ZTO與SiO2界面會產生界面電偶極(interface dipole)，因而減少了主動層與介電層(SiO2/ZTO)的導電帶能差(conduction band offset)，使Fowler–Nordheim 穿隧的機率上升，電子便可以順利通過SiO2。最後，閘極漏電流對於TFT操作的影響將被詳細的探討。
主題二探討溶液法製備的超薄主動層ZTO 薄膜電晶體的電子傳輸機制，量測方法是在固定溫度區間下由310 K降溫至77K量測ID-VG轉移曲線圖(transfer curve)。當環境溫度降低時，ID-VG轉移曲線會隨著溫度下降往的正閘極電壓方向偏移。ZTO中的導電機制與局域尾態(localized tail states)分布分別由兩個方式進行探討，1.根據二維Mott變程跳躍(variable range hopping ; VRH)理論進行汲極電流對應不同溫度(log ID vs. T-1/3)曲線進行線性擬合。2. 透過捕捉電荷密度的統計來估算局域尾態密度的變化。由2D Mott VRH理論線性擬合的結果發現ZTO薄膜的導電機制符合變程跳躍模型。由理論計算出的導帶底部能態密度為4.75×1020 cm-3eV-1。在ZTO中的高局域尾態密度是導致電子在室溫下呈現跳躍傳輸的重要因素。
主題三為製作薄膜電晶體型電荷擷取式記憶體，其元件疊層材料分別為p+ -Si(閘極)/SiO2(電荷阻隔層(blocking layer))/ Ni 奈米晶粒電荷擷取層(charge trapping layer)/ Al2O3電荷穿隧層(tunneling layer)/ZTO(主動層)/Al(源極/汲極)。元件可以透過施加閘極正偏壓40 V持續時間1秒的動作進行寫入(program)，此時，元件的臨界電壓會由初始位置往正閘極偏壓方向偏移約7 V，然而，此元件無法透過單純施加閘極負偏壓的方式使元件抹除(erase)，必須要在施加負偏壓的同時施予照射白光的動作，才能讓元件有效地回復到初始狀態。由元件經由照光後的次臨界斜率(subthreshold swing；S.S.)變化，可以得知光激發的帶電氧空缺會遷移至在Al2O3與ZTO的界面，而這個過程便可使被Ni電荷擷取層被捕獲的電子釋放出來，藉此達到抹除的目的。此主題將針對光電耦合抹除的特性進行詳細的探討與印證。
In this study, zinc-tin oxide (ZTO) was prepared by solution method as the active layer for thin film transistor (TFT). The microscopic electron conduction mechanism in the ultra-thin active layer and the causes of the gate-leakage current were discussed. Finally, the ZTO-TFT is fabricated into a charge trapping memory, and its write and erase characteristics are studied. The full text is divided into three parts:
In the first part, the variation in gate-leakage current due to the Fowler–Nordheim (FN) tunneling of electrons through a SiO2 dielectric layer in zinc-tin oxide thin film transistors (ZTO TFTs). It is shown that the gate-leakage current is not related to the absolute area of the ZTO active layer, but it is reduced by reducing the ZTO/SiO2 area ratio. The ZTO/SiO2 area ratio modulates the ZTO-SiO2 interface dipole strength as well as the ZTO-SiO2 conduction band offset, and subsequently affects the FN tunneling current through the SiO2 layer, which provides a route that modifies the gate-leakage current.
In the second part, carrier transport properties of solution processed ultra thin (4 nm) zin-tin oxide (ZTO) thin film transistor are investigated based on its transfer characteristics measured at the temperature ranging from 310K to 77K. As temperature decreases, the transfer curves show a parellel shift toward more postive voltages. The conduction mechanism of ultra-thin ZTO film and its connection to the density of band tail states have been substantiated by two approaches, including fitting logarithm drain current (log ID) to T-1/3 at 310K to 77K according to two-dimensional Mott variable range hopping theory and the extraction of density of localized tail states through the energy distribution of trapped carrier density. The linear dependency of log ID vs. T-1/3 indicates that the dominant carrier transport mechanism in ZTO is variable range hopping. The IV extracted value of density of tail states at the conduction band minimum is 4.75×1020 cm-3eV-1 through the energy distribution of trapped carrier density. The high density of localized tail states in the ultra thin ZTO film is the key factor leading to the room-temperature hopping transport of carriers among localized tail states.
The third study addresses that the nonvolatile charge trapping memory is demonstrated on a thin film transistor (TFT) using an solution processed ultra-thin (~7 nm) zinc tin oxide (ZTO) semiconductor layer with an Al2O3/Ni-nanocrystals (NCs) /SiO2 dielectric stack. A positive threshold voltage (VTH) shift of 7 V is achieved at gate programming voltage of 40 V for 1 s but the state will not be erased by applying negative gate voltage. However, the programmed VTH shift can be expediently erased by applying a gate voltage of -10 V in conjunction with visible light illumination for 1 s. It is found that the sub-threshold swing (S.S.) deteriorates slightly under light illumination, indicating that photo-ionized oxygen vacancies (Vo+ and/or Vo ++) are trapped at the interface between Al2O3 and ZTO, which assists the capture of electrons discharged from Ni NCs charge trapping layer. The light-bias coupling action and the role of ultra-thin ZTO thickness are discussed to elucidate the efficient erasing mechanism.
第一章 緒論 1
1-1 前言 1
1-2 研究動機 5
2-2-2薄膜電晶體的操作[17, 18] 10
第三章 研究方法與實驗步驟 17
3-1 實驗材料 17
3-2 實驗設備 19
3-3 分析儀器 21
第四章在氧化鋅錫(ZTO)薄膜電晶體中藉由ZTO/SiO2面積比調控Fowler Nordheim穿隧閘極漏電流 27
4-1 緒論 27
4-1-1 金屬-氧化物-半導體電流傳輸行為 29
4-1-2氧化物界面電偶極(Interface dipole) 32
4-2 元件製作與材料分析 34
4-2-1 元件製作 34
4-2-2 TEM分析 38
4-2-3 XPS分析 39
4-3 結果與討論 41
4-3-1 不同面積比之inkjet-printed 薄膜電晶體電性行為 41
4-3-2 p+ Si /SiO2/ Al (無沉積ZTO主動層元件)電性行為 45
4-3-3 Spin-coated 薄膜電晶體電性行為 48
4-3-4 電流式原子力顯微鏡(C-AFM)分析 51
4-3-5 閘極漏電流傳輸機制探討 52
4-3-6 閘極漏電流對薄膜電晶體的影響 55
4-4 結論 60
5-1 緒論 61
5-1-1 局域尾態密度分析 66
5-1-2電子跳躍式傳導(Hopping conduction) 70
5-2 元件製作 73
5-3 結果與討論 75
5-3-1 溫度對ZTO 薄膜電晶體的ID-VG特性曲線影響 75
5-3-2 二維Mott 變層跳躍傳輸理論分析 78
5-3-3 捕捉電荷密度計算 81
5-3-4 局域尾態密度分析 84
5-3-5 載子傳輸機制 86
5-4 結論 88
6-1 緒論 89
6-1-4 氧化鋅主動層薄膜電晶體型電荷擷取式記憶體 100
6-2 元件製作與材料分析 102
6-2-2 TEM分析 105
6-2-3 電性量測方法 106
6-3 電荷擷取式薄膜電晶體電性結果與討論 108
6-3-1 電荷擷取式薄膜電晶體之基本電性 108
6-3-2 真空環境下之電荷擷取式薄膜電晶體操作特性 112
6-3-3 電荷擷取式薄膜電晶體之寫入特性 113
6-3-4 電荷擷取式薄膜電晶體的抹除特性 114
6-3-6 電荷擷取式記憶體寫入與抹除操作機制探討 121
6-4 結論 125
第七章 總結 126
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