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系統識別號 U0026-0812200915373258
論文名稱(中文) 嵌入式一對多光碟備份系統之ESL分析設計與FPGA實現
論文名稱(英文) ESL analysis and FPGA implementation of an embedded duplicator system
校院名稱 成功大學
系所名稱(中) 電腦與通信工程研究所
系所名稱(英) Institute of Computer & Communication
學年度 97
學期 2
出版年 98
研究生(中文) 廖培鈞
研究生(英文) Pei-Chun Liao
學號 q3696410
學位類別 碩士
語文別 中文
論文頁數 94頁
口試委員 口試委員-黃俊岳
口試委員-侯廷偉
指導教授-陳中和
口試委員-謝明得
中文關鍵字 光碟備份 
英文關鍵字 duplicator 
學科別分類
中文摘要 一對多光碟備份系統的挑戰在於即時系統的特性,為了保持燒錄過程穩定必須確保傳輸速度,否則將導致燒錄失敗。因此如何評估、建立一個系統,保證提供給光碟機充足的頻寬,穩定的完成備份工作是一項重要的議題。

本論文使用ESL設計方式,在CoWare Platform Architect平台上建立一對多光碟備份系統。藉由模擬真實系統運作的方式,分析系統上各個元件設計對於整體效能的影響,如匯流排架構、DMA控制器、記憶體、IDE控制器。根據分析的結果建立一個數學頻寬方程式,將不同的硬體架構套入方程式,可以估算出一個等效頻寬,藉此評估在此系統架構下是否能提供充足的頻寬。

我們設計的RTL IDE Controller採用Distributed DMA及Ping-Pong Buffer架構,支援PIO Mode 0~4、UDMA Mode 0~2。此IDEC在TSMC 0.18um的製程下總共佔30K個邏輯閘。而在Xilinx XC2V8000 FPGA共用564個Flip-Flop及1436個LUT,最高時脈達到113Mhz。為了減少IDEC使用的硬體資源,我們用BRAM代替暫存器實現IDEC緩衝區,節省了Flip-Flop 78%及LUT 46%的使用量。我們實現了一對三的光碟備份系統在ARM Versatile發展平台,透過真實燒錄機,搭配自行開發的測試軟體,成功完成一對三的光碟備份。
英文摘要 In a duplicator system, one of the biggest challenges is the characterization of the real-time system. If the transfer speed is not fast enough, the DVD recorder may suffer buffer-under-run which leads to system failure. Thus, how to establish and evaluate a duplicator system with an adequate bandwidth for reliable disc duplicating task is an important issue.

This thesis presents an ESL methodology to analyze the duplicator system. We have established a virtual duplicator system in CoWare Platform Architect to simulate a real duplicator system. We have analyzed various components of the system design that affects the performance and have derived a bandwidth equation from the ESL analysis result. We can use this bandwidth equation to calculate the bandwidth and estimate whether the system architecture is suitable or not.

In the IDE Controller design, we use a distributed DMA and ping-pong buffer architecture to enhance the transfer throughput. The design supports PIO mode 0 to 4 and UDMA mode 0 to 2. It has been realized by TSMC 0.18um technology and the total gate count is 30K. It can run up to 113 MHz in Xilinx XC2V8000 FPGA implementation with 564 Flip-Flops and 1436 LUTs. In order to reduce the FPGA hardware resource, we substitute BRAM for registers to implement the IDEC buffer and the total Flip-Flop reduction is 78% and LUT is 46% respectively. We have implemented the duplicator system on the ARM Versatile platform and successfully completed a one-to-three disc backup through real DVD recorders and verification software.
論文目次 摘要 I
Abstract II
目錄 III
表目錄 VI
圖目錄 VII
第1章 序論 1
1.1 研究動機 1
1.2 研究貢獻 2
1.3 論文編排 2
第2章 背景知識與相關研究 3
2.1 ATA/ATAPI介面標準 3
2.1.1 規格演進 3
2.1.2 並列傳輸與串列傳輸 6
2.1.3 ATA/ATAPI裝置的控制暫存器 7
2.1.4 傳輸協定 8
2.1.5 PIO模式傳輸協定 10
2.1.6 Ultra DMA模式傳輸協定 11
2.2 光碟機簡介 15
2.2.2 光碟機的發展 16
2.2.3 光碟機存取光碟片模式 16
2.2.4 燒不死技術 19
2.2.5 光碟機指令標準 20
2.3 Electronic System Level(ESL)Design Concept 21
2.4 Related Work 22
2.4.1 數學推導法 22
2.4.2 系統模擬法 23
第3章 ESL方法之系統架構評估 25
3.1 System Description 26
3.2 Central Processing Unit(CPU) 27
3.3 System Bus 28
3.3.1 Arbiter Arbitration Policy 28
3.3.2 Ideal Bus Bandwidth 30
3.4 Direct Memory Access Controller(DMAC) 32
3.4.1 Traditional Centralized DMAC 32
3.4.2 Centralized DMAC with DMAC-Memory Bus 35
3.4.3 Distributed DMAC 37
3.4.4 Summary of DMA system design 40
3.5 Memory 42
3.6 IDE Controller(IDEC) 44
3.6.1 Single Buffer Design 45
3.6.2 Ping-Pong Buffer Design 46
3.7 Bandwidth equation 49
第4章 FPGA Implementation 51
4.1 Versatile平台的限制 52
4.2 RTL IDE Controller之實現 55
4.3 AHB Interface硬體架構 57
4.3.1 Slave Port & Register File 57
4.3.2 Master Interface & DMA Engine 58
4.4 緩衝區硬體架構 60
4.5 ATAPI硬體架構 62
4.5.1 Program IO(PIO)控制單元 65
4.5.2 Ultra DMA(UDMA)控制單元 66
4.6 合成結果 71
第5章 Verification 73
5.1 測試程式簡介 73
5.2 System Software 76
5.2.1 Boot Code 76
5.2.2 Exception Handlers 78
5.2.3 Device Driver 80
5.2.4 Middleware 83
5.3 Authoring Software(AS) 84
5.3.2 Recording Flow 85
5.4 驗證備份出來的光碟 87
第6章 結論與未來展望 89
6.1 結論 89
6.2 未來展望 89
參考文獻 91
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