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系統識別號 U0026-0812200915350967
論文名稱(中文) 基於砌塊式繪圖架構之三維繪圖著色引擎的設計、分析與實現
論文名稱(英文) Design, Analysis, and Implementation of a Rasterization Engine based on Tile-Based Rendering Architecture in 3D Graphics
校院名稱 成功大學
系所名稱(中) 電腦與通信工程研究所
系所名稱(英) Institute of Computer & Communication
學年度 97
學期 2
出版年 98
研究生(中文) 劉哲宇
研究生(英文) Jhe-Yu Liou
電子信箱 elvis@casmail.ee.ncku.edu.tw
學號 q3696107
學位類別 碩士
語文別 中文
論文頁數 78頁
口試委員 口試委員-賴永康
口試委員-楊佳玲
口試委員-蘇文鈺
指導教授-陳中和
口試委員-蕭勝夫
中文關鍵字 電腦圖學(繪圖)  Rasterization引擎  Tile-Based 繪圖管線 
英文關鍵字 Computer graphics  Rasterization engine  Tile-based rendering pipeline 
學科別分類
中文摘要 3D繪圖系統已經在桌上型電腦平台發展一段時日,所顯示出來的3D效果也相當的驚人。但由於需要大面積矽晶片以放置大量的運算元件,且擁有高溫、耗電等特性,使其無法被順利的整合在攜帶型電子產品之中。然而,隨著嵌入式系統的快速發展、硬體製程的進步、和消費性及攜帶性產品上對於3D繪圖的應用需求的大量增加,如何在這樣的產品中設計一個低成本的3D繪圖加速硬體已成為一項重要的課題。
一般的3D繪圖硬體中,依處理階段的不同,可分為前半部的Geometry engine跟後半部的Rasterization engine。本論文根據砌塊式繪圖架構為基礎,設計出一高效率之Rasterization engine。此引擎擁有以下幾點特點:使用tile-boundary skip traversal進行三角形掃描、使用barycentric coordinate轉換三角形座標進行內插、使用multi Z test和6D block texture cache等功能。這些特點使得RE硬體可以在維持一定繪圖品質的前提下,同時減少硬體設計面積跟提高硬體效能。本論文最後所完成之合成後RTL模型,可在QEMU全系統驗證平台下,以時脈200MHz和OpenGL ES應用程式軟體、Linux作業系統、geometry engine進行軟硬體協同模擬驗證,成功完成一可適用於嵌入式系統之3D繪圖引擎。
英文摘要 3D graphic rendering system for desktop has been developed for a long time and has the capability to show amazing 3D effect. However, this system is hard to be integrated with mobile electronic products because of its large-area requirement, high temperature, and high-power consumption. Due to the rapid development of embedded system and hardware technology, and increasing demand of 3D graphic applications for consumer electronic, how to design a low-cost 3D graphic accelerator has become an important issue.
A typical 3D graphic accelerator can be divided into a geometry engine and a rasterization engine by the different processing stages. In this thesis, a highly efficient rasterization engine based on tile-based architecture is proposed. This engine has incorporated the following architecture techniques: tile-boundary skip traversal, barycentric coordinate, multi Z test, and 6D block texture cache. With these features, we reduce the area cost and improve the performance of the rasterization engine we design. The rasterization engine when synthesized with TSMC 0.18um technology can run up to 200MHz. We also verify the entire 3D graphic accelerator net-list with OpenGL ES application in Linux OS under a full system simulation platform constructed with CoWare and QEMU.
論文目次 摘要 I
Abstract II
誌謝 III
目錄 IV
圖目錄 VII
表目錄 X
第1章 Introduction 1
1.1 Motivation 1
1.2 Contribution 1
1.3 Organization 2
第2章 Background and related work 3
2.1 3D Computer Graphic 3
2.2 Graphic application programming interface 4
2.2.1 OpenGL API 5
2.2.2 OpenGL ES 6
2.3 Conventional OpenGL pipeline 6
2.3.1 Geometry Stage 7
2.3.2 Rasterization Stage 9
2.4 Tile-Based rendering pipeline 14
2.5 Related work 15
2.5.1 Tile-based architecture 15
2.5.2 Conventional immediate mode architecture 16
第3章 Rasterization algorithm exploration 18
3.1 Edge function and Traversal 18
3.1.1 Edge function test 18
3.1.2 Traversal algorithm 20
3.1.3 Traversal method for tile-based architecture 22
3.1.4 A defect of tile-bounding skip traversal we proposed 24
3.1.5 Performance of tile bounding skip traversal 26
3.2 Interpolation 27
3.2.1 Plane equation 28
3.2.2 Plane equation with fixed-point calculation 29
3.2.3 Interpolation using barycentric coordinates 31
3.3 Anti-Aliasing(AA) 33
3.4 Texture mapping 38
3.5 Per-fragment operation 39
第4章 Architecture development 41
4.1 Texture cache 42
4.1.1 6D block texture cache 42
4.1.2 Simulation of texture cache 43
4.1.3 Summary of texture cache 45
4.2 Early depth test 46
4.2.1 Alpha test with early depth test 46
4.2.2 Data hazard in separated early depth test 49
4.2.3 Multi Z test 50
4.2.4 Simulation and summery of early depth test 52
4.3 RM Architecture summery 53
第5章 RTL implementation 54
5.1 Triangle setup 55
5.2 Rasterizer 56
5.3 Per-fragment operation 59
5.4 Summery of RTL implementation 60
第6章 Simulation and verification 61
6.1 Simulation platform 61
6.1.1 Simulation model 62
6.1.2 Full system simulation platform for RTL model 63
6.2 Verification methodology 66
6.3 Simulation and verification result 67
6.3.1 Simulation result 67
6.3.2 Verification result 70
第7章 Conclusion and future work 73
7.1 Conclusion 73
7.2 Future work 74
Reference 75
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