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系統識別號 U0026-0812200915301559
論文名稱(中文) 使用虛擬機器實現多視點繪圖處理器之全系統設計與模擬
論文名稱(英文) Full System Design and Simulation of a Multi-view Graphics Processor using QEMU
校院名稱 成功大學
系所名稱(中) 電腦與通信工程研究所
系所名稱(英) Institute of Computer & Communication
學年度 97
學期 2
出版年 98
研究生(中文) 沈協增
研究生(英文) Shye-Tzeng Shen
電子信箱 q3696428@mail.ncku.edu.tw
學號 q3696428
學位類別 碩士
語文別 中文
論文頁數 118頁
口試委員 口試委員-蕭勝夫
指導教授-陳中和
口試委員-蘇文鈺
口試委員-楊佳玲
口試委員-賴永康
中文關鍵字 軟硬體共同模擬  砌塊式繪圖法  電子系統層級設計  全系統模擬  多視點立體顯示 
英文關鍵字 full system simulation  software/hardware co-simulation  tile-based rendering  electronic system level design  multi-view 3D displays 
學科別分類
中文摘要 本論文提出一套適用於多視點繪圖處理器的全系統設計與模擬架構。此架構在硬體設計階段先建立一個完整的軟體開發環境,使軟硬體設計者在開發初期就能分別針對軟體應用程式或硬體演算法進行設計與評估。我們並導入虛擬機器與電子系統層級設計概念之虛擬平台,以全系統的驗證方法進行軟硬體共同設計與模擬。利用全系統模擬的方式,軟體設計者不但能夠快速開發驅動程式與應用程式,使軟體除錯的工作提前進行;而硬體設計者也可彈性配置虛擬平台上的硬體架構,並且有效率地調校整體系統的效能。
我們以ARM嵌入式系統做為欲模擬的平台環境。透過虛擬機器中所模擬之ARM系統來啟動Linux作業系統,並從繪圖應用程式與中介軟體層,到驅動程式與虛擬平台上的多視點繪圖子系統做溝通,完整地驗證Linux執行OpenGL ES應用程式的流程。此多視點繪圖處理器架構中包含砌塊式繪圖處理單元與DIBR硬體模組,其中砌塊式繪圖處理單元與市售之參考實作品做圖像比對的驗證,並可達到99%的相似度。最後,我們利用整套驗證架構來分析繪圖測試程式的特性,並進一步評估硬體效能。
英文摘要 In this thesis, a full system design and simulation framework suitable for a multi-view graphics processor is proposed. In the early stage of hardware design, we need to create a complete software development system to port benchmarks and evaluate the algorithms for software/hardware design. A full system design is used to allow software/hardware co-simulation at different levels of abstraction to introduce a virtual machine and an electronic system level design. Through a full system simulation platform, the software engineer can develop applications quickly and make early debugging; the hardware engineer also has a flexibility to configure the hardware architecture on the virtual platform; and we can tradeoff system performance in an efficient way.
An ARM embedded system is used as a full system simulation environment. The QEMU can emulate a typical ARM board with full system operating mode and boot an ARM Linux, and run OpenGL ES benchmarks through API layer, device driver, AHB interface, to multi-view graphics subsystem inside the virtual platform, which includes a tile-based rendering hardware and image synthesis module based on DIBR. The framework of this thesis is completely verified through the execution of 3D applications under full system simulation, and shows a similarity of 99% compared with reference images as a whole. Furthermore, the characterization of benchmarks and performance evaluation of a multi-view graphics processor are also analyzed.
論文目次 摘要 I
Abstract II
誌謝 III
目錄 IV
表目錄 VIII
圖目錄 IX
第1章 序論 1
1.1 Motivation 1
1.2 Contribution 3
1.3 Organization 4
第2章 背景知識與相關研究 5
2.1 3D Displays 5
2.1.1 Stereoscopic vision principle 5
2.1.2 Screen disparity 6
2.1.3 Brief overview of 3D perception 9
2.1.4 Types of Autostereoscopic display technologies 11
2.1.5 Two-view displays 12
2.1.6 Multi-view displays 13
2.2 3D Computer Graphics 13
2.2.1 3D effects 14
2.2.2 Rendering approaches 19
2.3 Graphics API standard 21
2.3.1 OpenGL 21
2.3.2 OpenGL ES 24
2.4 3D Rendering Pipeline 26
2.4.1 OpenGL ES pipeline 28
2.4.2 Tile-based rendering 30
2.4.3 Tile-based versus traditional rendering 31
2.5 QEMU and QEMU-SystemC 32
2.5.1 QEMU 32
2.5.2 QEMU-SystemC 35
2.6 Linux Device driver 36
2.6.1 Classes of devices and modules 37
2.6.2 File operations structure 38
2.6.3 I/O ports and I/O memory 39
2.6.4 Interrupt handling 39
2.7 Related work 40
2.7.1 Tile-based rendering 40
2.7.2 Other architecture designs 42
2.7.3 Simulation platform analysis 47
2.7.4 Multi-view algorithms 48
第3章 系統驗證架構之設計與實現 50
3.1 Preliminary 50
3.1.1 ESL design and TLM methodology 50
3.1.2 Full system simulation 54
3.1.3 CoWare Platform Architect 55
3.2 System framework overview 55
3.3 Software development 56
3.3.1 API middle layer 58
3.3.2 Back-end GPU simulator 61
3.3.3 OpenGL state information 62
3.3.4 Problems of the tile-based rendering approach 64
3.3.5 Implementation 65
3.4 Full system design and simulation 69
3.4.1 Overview of a multi-view graphics processor 70
3.4.2 Linux device driver design 71
3.4.3 Communication mechanism of full system simulation 73
3.4.4 Multi-view 3D data flow of full system simulation 75
3.5 Reference implementation 79
第4章 驗證環境與模擬結果 80
4.1 Verification environment 80
4.2 Verification and debug flow 81
4.3 Simulation results 84
4.4 Platform demonstration 89
第5章 負載特性與數據分析 91
5.1 Workload characterization 91
5.1.1 Detailed workload statistics 93
5.2 Architectural implications 102
5.2.1 The trade-off analysis of tile sizes 102
5.2.2 Memory bandwidth requirement 104
5.2.3 Experiment results of state management 107
5.3 Performance evaluation of full system simulation 108
第6章 結論與未來展望 111
6.1 Conclusion 111
6.2 Future work 112
參考文獻 113
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