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系統識別號 U0026-0812200915301558
論文名稱(中文) 基於砌塊式繪圖架構之三維繪圖幾何引擎設計、分析與實現
論文名稱(英文) Design, Analysis, and Implementation of a Geometry Engine Based on Tile-Based Rendering Architecture in 3D Graphics
校院名稱 成功大學
系所名稱(中) 電腦與通信工程研究所
系所名稱(英) Institute of Computer & Communication
學年度 97
學期 2
出版年 98
研究生(中文) 蔡順帆
研究生(英文) Shun-fan Tsai
電子信箱 shunfan@casmail.ee.ncku.edu.tw
學號 q3696426
學位類別 碩士
語文別 中文
論文頁數 111頁
口試委員 指導教授-陳中和
召集委員-蕭勝夫
口試委員-蘇文鈺
口試委員-賴永康
口試委員-楊佳玲
中文關鍵字 幾何引擎  電腦圖學(繪圖)  Tile-Based 繪圖管線 
英文關鍵字 Computer graphics  Geometry engine  Tile-based rendering pipeline 
學科別分類
中文摘要 本篇論文提出一個基於砌塊式繪圖管線架構之Geometry引擎。在3D電腦繪圖中,其所描述的場景由幾何單元所表示,也就是點、線、面,而這些幾何單元再依照光源的設定繪製出受不同光源影響的顏色圖像。而本篇論文則根據OpenGL ES 1.1的規格設計一個處理幾何單元運算的Geometry引擎並對並對其硬體架構作進一步的效能評估及分析。
在Geometry引擎的設計上,頂點處理器的架構切割成兩大級管線,有效地提升硬體使用率,減少面積;另外將perspective division模組設計於頂點處理器內,與未改善前的架構相比,整體面積降低58.6%。光源的指數計算部份以內插法的方式設計查表並將其實現成硬體,與未改善前的硬體合成面積相比,降低了17倍。為了減少匯流排頻寬,除了設計Culling模組外,我們提出ATT (Abandon Tiny Triangles)演算法刪除微小三角形,減少50%至60%不會繪製在螢幕上的三角形輸出量。此Geometry引擎在0.18um的製程下總共佔389K個邏輯閘,且能在200MHz的工作頻率下正確執行,並有瞬間最高7.407M Tri/sec的三角形運算效能。此硬體在QEMU結合CoWare的完整系統模擬環境下,能完整地驗證ARM嵌入式系統經由啟動Linux並執行OpenGL ES的應用程式。
英文摘要 This thesis presents a Geometry engine based on a tile-based rendering architecture. In 3D computer graphics, the scene is typically constructed from geometry objects made up from vertices, lines, or triangles, and these geometry objects are displayed in different types by various drawing modes. We design a Geometry engine that deals with the geometry calculation according to OpenGL ES 1.1 specifications and evaluate the performance of the hardware architecture.

In Geometry engine designing, we split the vertex processor into a 2-stage pipeline in order to reduce the overall area cost by increasing the hardware utilization efficiently. Comparing with the traditional architecture, we propose a new architecture that puts the perspective division model in the vertex processor. This design results in overall area reduction by 58.6%. For the lighting model, we use a linear interpolation index-reduced method to design the lookup table, and the synthesis area is nearly 17 times smaller than the hardware without modification. In order to reduce the bus traffic, we design a Culling model and propose an ATT (Abandon Tiny Triangles) algorithm to discard tiny triangles. The total triangle reduction is about 50% to 60% that would not be rendered on the screen. The Geometry engine has been realized by 0.18 um technology and the total gate count is 389K. It can run up to 200 MHz, and deliver the peak fill rate of 7.407M Tri/sec. It has been simulated and verified with OpenGL ES applications executed on Linux in an ARM embedded system modelled by a full system simulation platform which combines QEMU and an ESL tool.
論文目次 摘要 I
Abstract II
誌謝 III
目錄 IV
表目錄 VII
圖目錄 VIII
第1章 序論 1
1.1 Motivation 1
1.2 Contribution 2
1.3 Organization of Thesis 2
第2章 背景知識與相關研究 4
2.1 3D Computer Graphics 4
2.2 Graphics API 6
2.2.1 OpenGL 7
2.2.2 OpenGL ES 8
2.3 3D Graphics Rendering Pipeline 8
2.4 Overview of Geometry Engine 11
2.4.1 Transformation 13
2.4.2 Lighting 17
2.4.3 Primitive Assembly 20
2.4.4 Culling 21
2.4.5 Clipping 22
2.5 Concept of Electronic System Level 23
2.5.1 CoWare Platform Architecture 24
2.6 QEMU 25
2.7 Related work 26
2.7.1 Geometry Engine 26
2.7.2 Tile-Based Rendering 30
第3章 幾何引擎架構之設計 34
3.1 Tile-Based Rendering Architecture 34
3.2 Internal Models of Geometry Engine 36
3.2.1 Transformation Model 37
3.2.2 Lighting Model 43
3.2.3 Perspective Division Model 51
3.2.4 Primitive Assembly Model 54
3.2.5 Culling Model 57
3.2.6 Clipping Model 61
3.3 Tile Sorting Model in Tile-Based Rendering 66
3.3.1 Bounding Box Test 68
3.3.2 Overlap Test 69
3.3.3 Accuracy Problem of Tile Sorting Model 70
3.4 Geometry Engine Architecture 72
3.4.1 Vertex Processor Architecture 73
3.4.2 Triangle Processor in Geometry Engine 77
第4章 幾何引擎介面設計 79
4.1 Input Type of Geometry Engine 80
4.2 Output Type of Geometry Engine 81
4.3 Internal Registers of Geometry Engine 82
第5章 實驗環境與實驗結果 85
5.1 Design Models and SW/HW Verification 85
5.1.1 Simulation Framework 87
5.1.2 Geometry Engine Verification 87
5.2 Full System Simulation Platform 91
5.3 Experimental results 93
5.3.1 Synthesis Area Result of Geometry Engine (Gate count) 93
5.3.2 Number of Triangles after Culling and ATT Operations 96
5.3.3 Maximum Throughput of Geometry Engine 98
5.3.4 Cycle counts of Geometry Engine 99
5.3.5 Compared with other Geometry Engine 102
第6章 結論與未來展望 105
6.1 結論 105
6.2 未來展望 106
參考文獻 108
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