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系統識別號 U0026-0812200914374942
論文名稱(中文) 應用於MB-OFDM UWB接收機之CMOS射頻晶片的研製
論文名稱(英文) Design of CMOS RFICs for MB-OFDM UWB RF Receiver
校院名稱 成功大學
系所名稱(中) 電腦與通信工程研究所
系所名稱(英) Institute of Computer & Communication
學年度 96
學期 2
出版年 97
研究生(中文) 魏國峰
研究生(英文) Kuo-feng Wei
電子信箱 q3695153@mail.ncku.edu.tw
學號 q3695153
學位類別 碩士
語文別 中文
論文頁數 101頁
口試委員 指導教授-莊惠如
口試委員-洪子聖
口試委員-張盛富
口試委員-盧春林
口試委員-陳居毓
中文關鍵字 寬頻射頻接收機  降頻混頻器  射頻CMOS晶片 
英文關鍵字 RFICs  CMOS  UWB RF Receiver  down-conversion mixer 
學科別分類
中文摘要 本論文使用TSMC CMOS 0.18 µm製程設計應用於UWB接收機之射頻CMOS晶片及射頻前端電路的系統整合,包含3-5-GHz低電壓寬頻降頻混頻器與升頻混頻器、寬頻射頻接收機前端電路,及寬頻整合頻率合成器之CMOS射頻接收機。
3-5-GHz低電壓寬頻降頻混頻器採用切換轉導之雙平衡混頻架構。量測顯示: 在3-5 GHz的頻段內最高轉換增益為10-13 dB、最低雜訊介於7.5-8.3 dB、IIP3最大值約-7.5- -5 dBm、 input P1dB為-21- -16 dBm、LO-RF isolation大於50 dB、LO-IF isolation大於52 dB、RF-IF isolation大於50 dB、核心電路直流偏壓為1.2 V/2.1 mA,消耗功率為2.5 mW。3-5-GHz 升頻混頻器的部分採用折疊式之雙平衡混頻架構。量測顯示:最大轉換增益約5.3 dB,最大值OIP3約-0.5 dBm,LO-IF isolation 約為 37 dB, 直流消耗功率約 2.7 mW,操作電壓為Vdd 1.2 V。3-5-GHz 寬頻CMOS射頻接收機前端電路包含疊接架構之低雜訊放大器及I/Q降頻混頻器,並且使用單端輸入/雙端輸出的架構,省去巴倫平衡器設計以減少訊號衰減,量測顯示: 射頻接收機前端電路在3-5-GHz的頻段內最高轉換增益為18-27 dB、最低雜訊介於6-9.2 dB、IIP3最大值約-11- -5.5 dBm、LO-RF isolation大於51 dB、LO-IF isolation大於41 dB、RF-IF isolation大於10 dB、核心電路直流偏壓為1.8 V/26.2 mA、消耗功率為47.1 mW。3-5 GHz MB-OFDM UWB 整合頻率合成器之CMOS射頻接收機包含疊接組態之低雜訊放大器、結合電荷注入式之傳統單平衡式吉勃特混頻器及直接頻率合成架構之MB-OFDM UWB Mode-1 頻率合成器,量測顯示: 射頻接收機在3-5 GHz的頻段內最高轉換增益為17-24.1 dB、最低雜訊介於5.8-22.2 dB、IIP3最大值為-18- -12 dBm、RF-IF isolation約大於30 dB、核心電路直流偏壓為1.8 V/49 mA,消耗功率為88.2 mW。
英文摘要 This thesis presents the design on CMOS RFICs for MB-OFDM UWB RF Receiver. The RFICs are designed with TSMC 0.18 µm 1P6M standard CMOS fabrication process supplied. The first part presents 3-5-GHz low voltage broadband down-conversion and up-conversion mixers, the second part is 3-5-GHz broadband receiver front-end., and the third part is 3-5-GHz CMOS RF receiver integrated with frequency synthesizer for UWB MB-OFDM system.
The 3-5-GHz low voltage broadband CMOS down-conversion mixer employs a folded switched transconductor topology. Measured results are: a maximum conversion gain of 10-13 dB, minimum noise figure of 7.5-8.3 dB, maximum IIP3 of -7.5- -5 dBm, LO-RF isolation of about 50 dB, and a dc power only consumption of 2.5 mW at 1.2 V power supply. The 3-5-GHz low voltage broadband CMOS up-conversion mixer employs a folded switched topology. The mixer consists of a voltage-to-current (V-I) converter and a folded Gilbert switching quad. Measured results are: a maximum conversions gain of 5.3 dB, maximum OIP3 of -0.3 dBm, LO-IF isolation of about 37 dB, and a dc power only consumption of 2.7 mW at 1.2 V power supply.
The 3-5-GHz RF receiver front-end includes a LNA with a cascade topology and a I/Q mixer employing a single-balanced Gilbert cell topology. A pMOS current source is used to set transconductor and switching stage current independently. The quadrature LO signal generated by quadrature poly phase filter. Measured results are: a maximum conversion gain of 18-27 dB, minimum noise figure of 6-9.2 dB, maximum IIP3 of -11- -5.5 dBm, LO-RF isolation of about 51 dB, and a dc power only consumption of 47.1 mW at 1.8 V power supply. The 3-5-GHz CMOS RF receiver integrated with frequency synthesizer for UWB MB-OFDM system includes a LNA, a single-balanced Gilbert cell mixer and a MB-OFDM UWB CMOS mode-1 frequency synthesizer. Measured results are: a maximum conversion gain of 17-24.1 dB, minimum noise figure of 5.8-22.4 dB, maximum IIP3 of -18- -12 dBm, RF-IF isolation of about 30 dB, and a dc power only consumption of 88.2 mW at 1.8 V power supply.
論文目次 第一章 緒論 1
1.1超寬頻UWB研究背景與動機 1
1.2UWB現今發展概況 2
1.3UWB技術之未來展望與應用 3
1.4UWB系統頻帶規劃與系統架構簡介 5
1.4.1射頻接收端設計規格[5][6] 6
1.4.2發射機發射端設計規格[5][6] 7
1.5論文架構 7
第二章 3-5-GHz寬頻CMOS降頻與升頻混頻器 9
2.1混頻器簡介 9
2.23-5-GHz 寬頻CMOS切換轉導降頻混頻器 11
2.2.1切換轉導雙平衡混頻架構之簡介 11
2.2.2寬頻切換轉導混頻器架構實現與設計原理 11
2.3寬頻切換轉導混頻器設計流程 19
2.4量測考量 21
2.5模擬與量測結果 22
2.6結果與討論 27
2.73-5-GHz 寬頻CMOS升頻混頻器 29
2.7.1低電壓升頻混頻器架構之簡介 29
2.7.2低電壓升頻混頻器架構實現與設計原理 29
2.8寬頻升頻混頻器之設計流程 33
2.9量測考量 33
2.10模擬與量測結果 34
2.11結果與討論 39
第三章 3-5-GHz寬頻CMOS射頻接收機前端電路 41
3.1寬頻CMOS接收機前端電路之簡介 41
3.2寬頻CMOS射頻接收機前端電路之架構實現與設計原理 42
3.2.1低雜訊放大器之架構實現與設計原理 42
3.2.2降頻混頻器架構實現與設計原理 47
3.2.3多相位濾波器設計原理 48
3.3寬頻CMOS射頻接收機前端電路之設計流程 50
3.4量測考量 51
3.5模擬與量測結果 52
3.6問題與討論 57
第四章 3-5-GHz整合頻率合成器之寬頻CMOS射頻接收機 61
4.1寬頻CMOS射頻接收機之簡介 61
4.2寬頻CMOS射頻接收機之架構實現與設計原理 62
4.2.1低雜訊放大器之架構實現與設計原理 62
4.2.2降頻混頻器架構實現與設計原理 66
4.2.3頻率合成器實現與設計原理 67
4.3模擬與量測結果 75
4.4結果與討論 80
第五章 結論 83
參考文獻 85
附錄A 直接轉換降頻接收機之二次交互調變失真與二次截斷點之探討 89
A.1二次交互調變失真之簡介 89
A.2二次交互調變失真之分析與探討 90
A.3轉導混頻器之IP2與直流偏移之探討及分析 93
A.3.1單平衡與雙平衡混頻器之IP2分析 94
A.3.2共源極組態RF輸入轉導級交互調變失真之分析 98
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