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系統識別號 U0026-0812200914024122
論文名稱(中文) 應用於UWB收發機之CMOS射頻前端電路的研製
論文名稱(英文) Research on CMOS Front-end RFICs for UWB Transceiver
校院名稱 成功大學
系所名稱(中) 電腦與通信工程研究所
系所名稱(英) Institute of Computer & Communication
學年度 95
學期 2
出版年 96
研究生(中文) 陳奕帆
研究生(英文) Yi-Fan Chen
電子信箱 Q3694160@mail.ncku.edu.tw
學號 q3694160
學位類別 碩士
語文別 中文
論文頁數 73頁
口試委員 指導教授-莊惠如
口試委員-洪子聖
口試委員-張盛富
口試委員-張嘉展
口試委員-盧春林
中文關鍵字 射頻前端電路  收發機  寬頻 
英文關鍵字 UWB  CMOS  RFIC  Front-end 
學科別分類
中文摘要 本論文主要針對UWB射頻收發機CMOS晶片進行研究與製作,主要規劃整合收發機前端接收與發射的放大電路。論文中首先介紹UWB系統架構。循以上系統需求,規劃收發機前端電路的特性要求與實現電路。首先針對收發機接收端的低雜訊放大器進行研製,目標以低消耗功率與低雜訊為目標。再者設計收發機發射端所需之驅動放大器以供應系統需求。最後探討收發機的切換開關,利用一個CMOS單極雙擲架構之T/R切換開關,將先前電路,整合為收發機前端電路晶片。以上晶片,皆採用國家晶片中心(CIC)所提供的TSMC 0.18 μm製程實現。
在3-5-GHz CMOS低雜訊放大器方面,量測結果為輸入返回損耗大於9.3 dB、輸出返回損耗大於10.4 dB、增益大於8.5 dB、隔離度大於27.4 dB,IIP3為 -7.5- -3.8 dBm、Input P1dB為-14.7- -10.2 dBm。在3-5-GHz CMOS驅動放大器方面,量測結果為,增益大於13.3 dB,輸入返回損耗大於10.9dB,輸出返回損耗大於15.3 dB ,以及隔離度大於31.3 dB。Output P1dB > -1.2 dBm、OIP3 > 6.8 dBm、PAE > 6 %@1-dB compression point,總消耗功率為12 mW。在3-5-GHz CMOS前端電路方面,接收模式的量測結果為,增益大於4.6 dB、輸入返回損耗大於10.3 dB、輸出返回損耗大於7 dB、總消耗功率為18 mW;;發射模式的量測結果為:S21大於4.5 dB、輸入返回損耗大於9.5 dB、輸出返回損耗大於8.3 dB、總消耗功率為12 mW。
英文摘要 This thesis is designed for CMOS RFICs of the UWB Transceiver. The main work has combined amplifier circuits of receiver and transmitter to form a transceiver. For a start, it introduces the framework of the UWB systems. Then it planes the characteristic of front-end circuits of transceiver to meet the requirement of the UWB system. First, it design a low noise amplifier of the receiver which is low power consumption and low noise. Then, realize a driving amplifier of the transmitter for the demand of the UWB system. Finally, this thesis adopts the T/R switch of the transceiver that apply the frame of CMOS SPDT, integrate previous circuit with the RF front-end chip of the transceiver. These RFICs are fabricated with a TSMC 0.18-μm CMOS process supported by the CIC.
The measured results of 3-5-GHz CMOS low noise amplifier is:An input return loss is greater than 9.3 dB, an output return loss is greater than 10.4 dB, a gain is greater than 8.5 dB, an isolation is greater than 27.4 dB, show an IIP3 of -7.5- -3.8 dBm, an input P1dB of -14.7- -10.2 dBm. The measured results of 3-5-GHz CMOS driving amplifier is:A gain is greater than 13.3 dB, an input return loss is greater than 10.9 dB, an output return loss is greater than 15.3 dB, an isolation is greater than 31.3 dB, an Output P1dB is greater than -1.2 dBm, an OIP3 is greater than 6.8 dBm, and show a PAE of 1-dB compression point is greater than 6 pct., a power consumption is 12 mW. The measured results of receive-mode (Rx-mode) of 3-5-GHz CMOS front-end RFICs is:A gain is greater than 4.6 dB, an input return loss is greater than 10.3 dB, an output return loss is greater than 7 dB, and power consumption is 18 mW. The measured results of transmit-mode (Tx-mode) of 3-5-GHz CMOS front-end RFICs is:A gain is greater than 4.5 dB, an input return loss is greater than 9.5 dB, an output return loss is greater than 8.3 dB, and power consumption is 12 mW.
論文目次 第一章 緒論 1
1.1 研究背景與動機 1
1.2 UWB系統簡介 2
1.2.1 MB-OFDM UWB實體層技術 4
1.2.2 DS-UWB實體層 5
1.3 論文架構 7
第二章 寬頻 CMOS低雜訊放大器研製 9
2.1 主動電路之雜訊介紹 9
2.2 寬頻低雜訊放大器探討 13
2.3 3-5-GHZ CMOS 低雜訊放大器之研製 19
2.3.1 電路架構 19
2.3.2 設計流程 19
2.3.3 模擬與量測 21
2.3.4 結果與討論 23
第三章 寬頻 CMOS驅動放大器研製 25
3.1 驅動放大器簡介 25
3.2 放大器線性度探討 28
3.3 3-5-GHZ CMOS 驅動放大器之研製 36
3.3.1 電路架構考量 36
3.3.2 設計流程 37
3.3.3 模擬與量測 38
3.3.4 結果與討論 41
第四章 3-5-GHZ寬頻 CMOS收發機前端電路整合研製 43
4.1 整合電路簡介與規劃 43
4.2 收發機T/R切換開關探討 47
4.3 3-5-GHZ CMOS 前端電路之研製 52
4.3.1 電路架構 52
4.3.2 設計流程 54
4.3.3 模擬與量測 56
4.3.4 結果與討論 62
第五章 結論 63
參考文獻 65
附錄A 3-8-GHZ CMOS 低雜訊放大器之研製 67
A.1 電路架構 67
A.2 設計流程 68
A.3 模擬與量測 70
A.4 結果與討論 72
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