進階搜尋


 
系統識別號 U0026-0812200912092275
論文名稱(中文) 漸進式設計流程:應用於H.264 baseline profile RDO 編碼器之積體電路設計
論文名稱(英文) A Progressive Design Flow and Its Application to H.264 BP RDO Encoder VLSI Design
校院名稱 成功大學
系所名稱(中) 資訊工程學系碩博士班
系所名稱(英) Institute of Computer Science and Information Engineering
學年度 94
學期 2
出版年 95
研究生(中文) 蘇育褘
研究生(英文) Yu-Hui Su
學號 P7693435
學位類別 碩士
語文別 中文
論文頁數 54頁
口試委員 指導教授-蘇文鈺
口試委員-蔣迪豪
口試委員-楊家輝
口試委員-陳培殷
口試委員-陳中和
中文關鍵字 協同設計  協同驗證  FPGA  H.264  RDO  IC 設計流程  漸進式的  C模型  多執行緒 
英文關鍵字 RDO  H.264  FPGA  IC design flow  progressive  C model  multi-thread  co-design  co-verification 
學科別分類
中文摘要   隨著製程技術的進步,單一晶片可容納的邏輯閘數目已遠遠超乎過去的想像。而數位時代的來臨,越來越多高複雜度的IC設計需求油然而生,此時傳統的IC設計方法已趕不上市場需求的速度,欲突破此一困境,需要由設計方法進行改造,提高電路設計的正確性,增加設計及驗證速度,以縮短產品上市時間。
  本文提出一個新的漸進式硬體設計驗證流程,此流程從最一開始的C model到最後電路在FPGA上進行大量資料驗證皆涵蓋其中。整個流程以電路驗證做為設計上之基本考量,將電路所需要的測試資料,以及結果、乃至結果之比對,皆整合進本流程當中,而整個流程之產出,皆會在下一個階段被利用,而不會造成資源浪費。最後,我們以H.264視訊編碼系統為例,講解如何將本流程套用至實際應用當中。在我們的經驗中,這樣的設計流程能夠大大的減低耗費在驗證以及除錯等佔據了大部分產品開發的時間。

英文摘要   As the process technology growing, the total gate count in a single chip has farther beyond our imagination. Comes the digital age, there are more and more complex IC design requirements. In this situation, traditional IC design flow can not follow the highly growing and demanding requirements. For design breakthrough, we must make improvements from our design methodology, to increase the reliability, and speed up design and verification time, to cut down time to market.
  In this thesis, a novel progressive hardware design/verification flow is proposed. This flow covers from the beginning of algorithm/system modeling/partitioning with C language model to the end of design verification on FPGA. Design verification is the main issue of this flow. The result produced in each design phase of the proposed design flow can be used in the verification of the next design phase. In addition, generating test vectors and comparing the results on both simulation model and real circuit in FPGA are also achieved during this flow. At the end of this thesis, we take currently popular video encoding system – H.264 as a design example, to explain this novel design flow. In our experiences the proposed design flow greatly reduces the time spent on verification and debugging which occupy most of the design time of a product.

論文目次 致謝 I
摘要 II
ABSTRACT III
目錄 V
表目錄 VII
圖目錄 VIII
CHAPTER 1 INTRODUCTION - 1 -
CHAPTER 2 DESIGN FLOW - 4 -
2.1 SOFTWARE MODEL REFINEMENT - 4 -
2.2 ARCHITECTURE SIMULATOR - 5 -
2.3 HDL CODING/SIMULATION - 9 -
2.4 SW/HW CO-VERIFICATION/CO-EMULATION - 9 -
CHAPTER 3 APPLYING THE DESIGN FLOW TO H.264 - 12 -
3.1 軟硬體共同架構設計 - 13 -
3.1.1 RD cost 公式 - 13 -
3.1.2 Intra Prediction演算法 - 16 -
3.2 設計MULTITHREADING HARDWARE ARCHITECTURE SIMULATOR (MHAS)的方法 - 20 -
3.2.1 Software environment initialize - 21 -
3.2.2 Thread communication - 22 -
3.2.3 Bus structure - 23 -
3.3 HARDWARE電路設計 - 26 -
3.3.1 Over All - 26 -
3.3.2 Main Memory - 27 -
3.3.3 Intra Prediction - 28 -
3.3.4 Deblocking - 38 -
3.4 HW/SW CO-VERIFICATION - 41 -
3.4.1 程式部分 - 44 -
3.4.2 電路部分 - 45 -
3.5 整合驗證過程 - 46 -
CHAPTER 4 RESULT AND CONCLUSION - 48 -
4.1 以MHAS/E設計電路的好處 - 49 -
4.2 缺點與改進 - 51 -
4.3 FUTURE WORK - 52 -
參考文獻 - 53 -
參考文獻 [1]電子工程專輯
http://www.eettaiwan.com/ARTP_8800411440_617723.HTM
[2] “Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T Rec. H.264 | ISO/IEC 14496-10 AVC)”, in Joint Video Team, Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG, JVT-G050, Mar. 2003.
[3] TW, GJ. S, Gisle Bjontegaard, Ajay Luthra, “Overview of the H.264/AVC Video Coding Standard”, IEEE Transactions on Circuits and System for Video Technology, Vol. 13, No. 7, July 2003
[4]Wayne Wolf, “A Decade of Hardware/Software Codesign”, Computer, pp. 38-43, April 2003
[5] Chamberlain, R. Lockwood, J. Gayen, S. Hough, R. Jones, P., “Use of a soft-core processor in a hardware/software codesign laboratory”, Microelectronic Systems Education, 2005. (MSE '05). Proceedings. 2005 IEEE International Conference on, pp. 97- 98, June 2005.
[6] Peng Liu, “Hardware/software codesign for embedded RISC core”, Media Processors 2002, Sethuraman Panchanathan, V. Michael Bove, Jr., Subramania I. Sudharsanan, Editors, December 2001, pp. 21-28
[7]G. J. Sullivan and T. Wiegand, “Rate-distortion optimization for video compression,” IEEE Signal Process. Mag., vol. 15, no. 11, pp. 74–90, Nov. 1998.
[8] T. Wiegand, H. Schwarz, A. Joch, F. Kossentini, and G. J. Sullian,“Rate-constrained coder control and comparison of video coding standards,”IEEE Trans. Circuits Syst. Video Technol., vol. 13, no. 7, pp.688–703, Jul. 2003.
[9] T. Wiegand, M. Lightstone, D. Mukherjee, T. G. Campbell, and S. K. Mitra, “Rate-Distortion Optimized Mode Selection for Very Low Bit Rate Video coding and Emerging H.263 Standard,” IEEE Trans. on Circuits and System for Video Technology, vol. 6, no. 2, pp. 182-190, Apr. 1996.
[10] C. P. Wang, and C. H. Chen, “An Architecture Design of De-blocking Filter in H.264/AVC for Real-time High Definition Video Processing”, July 2006
論文全文使用權限
  • 同意授權校內瀏覽/列印電子全文服務,於2008-08-25起公開。
  • 同意授權校外瀏覽/列印電子全文服務,於2008-08-25起公開。


  • 如您有疑問,請聯絡圖書館
    聯絡電話:(06)2757575#65773
    聯絡E-mail:etds@email.ncku.edu.tw