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系統識別號 U0026-0812200912072972
論文名稱(中文) 低電壓,低雜訊CMOS混頻器與應用於Ka頻帶寬頻二極體混頻器之研製
論文名稱(英文) Design and Implementation of Low-Voltage, Low-Noise CMOS Mixer and A Monolithic Broadband Doubly Balanced Ka-Band Diode Mixer
校院名稱 成功大學
系所名稱(中) 微電子工程研究所碩博士班
系所名稱(英) Institute of Microelectronics
學年度 94
學期 2
出版年 95
研究生(中文) 林志明
研究生(英文) Chih-Ming Lin
電子信箱 tailinhome@yahoo.com.tw
學號 q1693121
學位類別 碩士
語文別 中文
論文頁數 82頁
口試委員 指導教授-王永和
指導教授-蔡宗祐
口試委員-洪茂峰
口試委員-王瑞祿
口試委員-盧春林
中文關鍵字 低電壓  混頻器  MMIC  寬頻  Ka頻帶 
英文關鍵字 Low Voltage  Mixer  MMIC  broadband  Ka-band 
學科別分類
中文摘要 本文主要是將傳統式雙平衡星狀混頻器,利用一個180度的hybrid,以及兩個Marchand balun設計一可操作在Ka-band之新穎雙平衡星型混頻器電路,相較以往常用的星型混頻器結構,本文所提出新的電路架構,將針對以往兩組交叉型balun對IF端佈局所產生的電感效應進行改良,新的電路架構方式,使得IF端佈局更為簡潔,IF端可直接將訊號取出,無須使用airbridge以及多餘的微帶線所造成的電感效應,且大幅減小電路之面積。
目前對行動通訊系統的資料傳輸速率要求越來越高,而3G系統實際所能提供的最高速率也只有384kbps,不能滿足實際需求,因此在3G系統還沒有大規模投入商用的情況下,國內外行動通訊領域的專家已經開始進行4G(或3G+)系統的研發工作。接著設計一操作在8GHz的頻段且提供0.8V的低電壓操作的CMOS降頻混頻器,主要應用在低中頻系統架構,可避免零中頻架構的些許缺點。同時,現今通訊系統產品漸以平衡式或差動式的電路為設計,因此在論文中也將討論平衡式元件的量測方法以及實作電路。




英文摘要 The proposed Ka-Band mixer consists of a 180-degree hybrid circuit and two identical Marchand baluns. The 180-degree hybrid circuit comprises a Lange coupler and 90-degree microstrip line. According to the phase relationship in this proposed doubly-balanced star mixer, the diodes’ arrangement instead of a star quad diode is used. Then, the IF port presents a virtual ground to RF and LO signals to ensure LO-IF and RF-IF isolation. Furthermore, compared with the conventional star mixer, the IF signals can be easily extracted from the common node of the diodes. That is more flexible in layout design and also decreases the IF inductance because the consideration of the undesired coupling from baluns in IF port is not necessary.
The requirements for very high data rates make the significant progress of 4G communication systems. In this work, a down-conversion active CMOS mixer using balanced and differential structure that operates at 8GHz at the bias voltage of 0.8V is proposed for the application to Low-IF receiver which can overcome the disadvantages of the Zero-IF receiver. The circuit is implemented by the 0.18µm CMOS process. The circuit performance will be discussed.




論文目次 第一章 緒論……………………………………………………………1
1.1研究動機與背景……………………………………………………1
1.2混頻器發展…………………………………………………………2
1.3章節概敘……………………………………………………………3
第二章 收發機架構與基礎理論 ………………………………………4
2.1 接收系統架構簡介…………………………………………………4
2.1.1 接收機系統考量…………………………………………………4
2.1.2 超外差式接收機…………………………………………………5
2.1.3 直接降頻式接收機………………………………………………6
2.1.4 低中頻式接收機…………………………………………………9
2.2 基礎理論……………………………………………………………12
2.2.1 雜訊指數…………………………………………………………12
2.2.2 動態範圍…………………………………………………………15
2.2.3 輸入端3階交錯點………………………………………………16
2.3 混頻器的規格參數………………………………………………19
2.3.1 轉換增益/損耗…………………………………………………19
2.3.2 隔離度(Isolation)……………………………………………20
第三章 低電壓,低雜訊摺疊式混頻器………………………………21
3.1 架構簡介……………………………………………………………21
3.2 設計原理……………………………………………………………25
3.2.1設計緣由與目的…………………………………………………25
3.2.2 電路架構…………………………………………………………26
3.2.3 設計流程圖………………………………………………………29
3.3 模擬結果……………………………………………………………30
3.4 電路佈局……………………………………………………………34
3.5 量測結果……………………………………………………………35
3.5.1 平衡轉非平衡被動電路…………………………………………35
3.5.2 測試電路板………………………………………………………38
3.5.3 小訊號量測結果…………………………………………………39
3.6 結果討論……………………………………………………………42
第四章 星狀雙平衡式混頻器…………………………………………44
4.1架構簡介……………………………………………………………44
4.2 設計原理……………………………………………………………49
4.2.1 設計緣由與目的…………………………………………………49
4.2.2 電路架構…………………………………………………………50
4.2.3 設計流程圖………………………………………………………53
4.3 模擬結果……………………………………………………………54
4.4 電路佈局……………………………………………………………58
4.5 量測結果……………………………………………………………59
4.6 結果討論……………………………………………………………63
第五章 結論……………………………………………………………64


參考文獻……………………………………………………………66

作者簡介……………………………………………………………70
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